Datasheet AK5704 (Asahi Kasei Microdevices) - 8

[AK5704]
5.4. Pin State In Power-down Mode
Register Power-down No. Pin Name I/O Pin Power-down (PDN pin = “L”) (PDN pin = “H”) 1 CAD I Hi-z ← 2 SCL I Hi-z ← 3 SDA I/O Hi-z ← 4 WINTN O Hi-z “H” (TVDD) 5 SDTO1 O Pull-down to VSS2 by 49kΩ (typ.) “L” (VSS2) TDMIN I 6 Pull-down to VSS2 by 49kΩ (typ.) “L” (VSS2) SDTO2 O 7 LRCK I/O Pull-down to VSS2 by 49kΩ (typ.) “L” (VSS2) 8 BCLK I/O Pull-down to VSS2 by 49kΩ (typ.) “L” (VSS2) 9 MCKO O Pull-down to VSS2 by 49kΩ (typ.) “L” (VSS2) 10 MCKI I Hi-z ← 11 VDD12 - Pull-down to VSS2 by 700Ω (typ.) Normal Operation 12 VSS2 - - - 13 TVDD - - - 14 PDN I Hi-z ← 15 VREF O Hi-z ← Pull-down to VSS1 by 260Ω (typ.) @AVDD=3.3V 16 VCOM O ← Pull-down to VSS1 by 265Ω (typ.) @AVDD=1.8V 17 VSS1 - - - 18 AVDD - - - 19 MPWR2 O Hi-z ← 20 AIN2B- I Hi-z ← AIN2B+ I 21 Hi-z ← DMCLK2 O 22 AIN2A- I Hi-z ← AIN2A+ I 23 Hi-z ← DMDAT2 I 24 AIN1B- I Hi-z ← AIN1B+ I 25 Hi-z ← DMCLK1 O 26 AIN1A- I Hi-z ← AIN1A+ I 27 Hi-z ← DMDAT1 I 28 MPWR1 O Hi-z ← 019000890-E-00 2019/02 - 8 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE