Datasheet ADL5335 (Analog Devices) - 8

ADL5335 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 K S L IO CS SC SD VPO 61 51 41 31 VPOS1 1 12 FA RFIN– 2 ADL5335 11 ENBL RFIN+ 3 TOP VIEW 10 RFOUT (Not to Scale) VPOS2 4 9 GND5 5 6 7 8 ND1 ND2 ND3 ND4 G G G G NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A GROUND PLANE WITH A LOW THERMAL AND
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ELECTRICAL IMPEDANCE.
163 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 13 VPOS1, VPOS2, Power Supplies. Separately decouple each power supply pin using 100 pF and 0.1μF capacitors. VPOS3 2, 3 RFIN−, RFIN+ RF Negative and Positive Inputs. These pins have a 50 Ω differential input pair and are internally ac- coupled. 5 to 9 GND1, GND2, GND3, Ground. Connect these ground pins to a low impedance ground plane. GND4, GND5 10 RFOUT RF Output. This pin has a 50 Ω single-ended output and is internally ac-coupled. 11 ENBL Enable. A logic high on this pin (1.8 V logic) enables operation and a logic low on this pin puts the device in a low power sleep mode. 12 FA Fast Attack. A logic high on this pin (1.8 V logic) decreases the programmed gain by an additional 2 dB, 4 dB, 8 dB, or 16 dB. The fast attack attenuation step is defined by the last two bits of an 8-bit programming byte that is written to the device via the SPI. When FA returns to a logic low, the gain returns to its normal programmed level. When not using the fast attack function, tie the FA pin to ground. 14 SDIO Serial Data Input/Output (SDIO), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack attenuation (−2 dB, −4 dB, −8 dB, or −16 dB). 15 SCLK Serial Clock (SCLK), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack attenuation (−2 dB, −4 dB, −8 dB, or −16 dB). 16 CS Chip Select Bar (CS), 1.8 V Logic. The gain and fast attack attenuation levels are programmed using eight bits (Register Address 0x100). The 24-bit write consists of an R/W bit, a 15-bit register address, and the eight bits of data. The first six bits of data set the gain and the last two bits set the fast attack attenuation (−2 dB, −4 dB, −8 dB, or −16 dB). EP Exposed Pad. Connect the exposed pad to a ground plane with a low thermal and electrical impedance. Rev. 0 | Page 8 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DIGITAL LOGIC TIMING SPI Timing Diagram ABSOLUTE MAXIMUM RATINGS THREMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE DIGITAL INTERFACE OVERVIEW Serial Peripheral Interface (SPI) Fast Attack (FA) APPLICATIONS INFORMATION BASIC CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE