Datasheet LTC1863, LTC1867 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 8-Channel 200ksps ADCs |
| Seiten / Seite | 18 / 9 — TIMING DIAGRAMS. t1 (For Short Pulse Mode). t2 (SDO Valid Before SCK. t3 … |
| Revision | E |
| Dateiformat / Größe | PDF / 470 Kb |
| Dokumentensprache | Englisch |
TIMING DIAGRAMS. t1 (For Short Pulse Mode). t2 (SDO Valid Before SCK. t3 (SDO Valid Hold Time After SCK
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1863/LTC1867
TIMING DIAGRAMS t1 (For Short Pulse Mode) t2 (SDO Valid Before SCK
↑
), t3 (SDO Valid Hold Time After SCK
↓
)
t1 t2 CS/CONV 50% 50% SCK 0.4V t3 2.4V SDO 0.4V
t5 (SDI Setup Time Before SCK
↑
), t4 (SDO Valid After CONV
↓
) t6 (SDI Hold Time After SCK
↑
)
t4 t t 5 6 CS/CONV 2.4V 0.4V SCK Hi-Z 2.4V SDO 2.4V 2.4V 0.4V SDI 0.4V 0.4V
t7 (SLEEP Mode Wake-Up Time) t8 (BUS Relinquish Time)
t7 t8 SCK 50% 2.4V CS/CONV SLEEP BIT (SLP = 0) READ-IN 90% Hi-Z CS/CONV 50% SDO 10% 1867 TD
APPLICATIONS INFORMATION Overview
The LTC1863/LTC1867 are complete, low power multi- During the conversion, the internal differential 16-bit plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci- capacitive DAC output is sequenced by the SAR from tive successive approximation A/D converter, a precision the most significant bit (MSB) to the least significant bit internal reference, a configurable 8-channel analog input (LSB). The input is successively compared with the binary multiplexer (MUX) and a serial port for data transfer. weighted charges supplied by the differential capacitive Conversions are started by a rising edge on the CS/CONV DAC. Bit decisions are made by a low-power, differential input. Once a conversion cycle has begun, it cannot be comparator. At the end of a conversion, the DAC output restarted. Between conversions, the ADCs receive an input balances the analog input. The SAR contents (a 12-/16-bit word for channel selection and output the conversion data word) that represent the analog input are loaded into result, and the analog input is acquired in preparation for the 12-/16-bit output latches. the next conversion. In the acquire phase, a minimum time of 1.5µs will provide enough time for the sample-and-hold capacitors to acquire the analog signal. Rev. E For more information www.analog.com 9 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Dynamic Accuracy Analog Input Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Typical Connection Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Related Parts
TIMING DIAGRAMS t1 (For Short Pulse Mode) t2 (SDO Valid Before SCK
↑
), t3 (SDO Valid Hold Time After SCK
↓
)
t1 t2 CS/CONV 50% 50% SCK 0.4V t3 2.4V SDO 0.4V
t5 (SDI Setup Time Before SCK
↑
), t4 (SDO Valid After CONV
↓
) t6 (SDI Hold Time After SCK
↑
)
t4 t t 5 6 CS/CONV 2.4V 0.4V SCK Hi-Z 2.4V SDO 2.4V 2.4V 0.4V SDI 0.4V 0.4V
t7 (SLEEP Mode Wake-Up Time) t8 (BUS Relinquish Time)
t7 t8 SCK 50% 2.4V CS/CONV SLEEP BIT (SLP = 0) READ-IN 90% Hi-Z CS/CONV 50% SDO 10% 1867 TD
APPLICATIONS INFORMATION Overview
The LTC1863/LTC1867 are complete, low power multi- During the conversion, the internal differential 16-bit plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci- capacitive DAC output is sequenced by the SAR from tive successive approximation A/D converter, a precision the most significant bit (MSB) to the least significant bit internal reference, a configurable 8-channel analog input (LSB). The input is successively compared with the binary multiplexer (MUX) and a serial port for data transfer. weighted charges supplied by the differential capacitive Conversions are started by a rising edge on the CS/CONV DAC. Bit decisions are made by a low-power, differential input. Once a conversion cycle has begun, it cannot be comparator. At the end of a conversion, the DAC output restarted. Between conversions, the ADCs receive an input balances the analog input. The SAR contents (a 12-/16-bit word for channel selection and output the conversion data word) that represent the analog input are loaded into result, and the analog input is acquired in preparation for the 12-/16-bit output latches. the next conversion. In the acquire phase, a minimum time of 1.5µs will provide enough time for the sample-and-hold capacitors to acquire the analog signal. Rev. E For more information www.analog.com 9 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Dynamic Accuracy Analog Input Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Typical Connection Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Related Parts