Datasheet AD7949-EP (Analog Devices) - 8

AD7949-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D 3 2 D 1 0 N N V I I NI NI 0 9 8 7 6 2 1 1 1 1 VDD 1 15 VIO REF 2 14 SDO AD7949-EP REFIN 3 13 SCK TOP VIEW GND 4 12 (Not to Scale) DIN GND 5 11 CNV 6 7 8 9 0 1 4 5 6 7 N M I NI NI NI O C NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE
4 00
SOLDERED TO THE SYSTEM
2-
GROUND PLANE.
982 0 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 20 VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for 2.5 V output, the minimum should be 3.0 V. When using the internal reference for 4.096 V output, the minimum should be 4.5 V. 2 REF AI/O Reference Input/Output. See the AD7949 data sheet. When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as close to REF as possible. See the AD7949 data sheet. 3 REFIN AI/O Internal Reference Output/Reference Buffer Input. See the AD7949 data sheet. When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as described above. 4, 5 GND P Power Supply Ground. 6 to 9 IN4 to IN7 AI Channel 4 through Channel 7 Analog Inputs. 10 COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or VREF/2 V. 11 CNV DI Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled. 12 DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion. 13 SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion. 14 SDO DO Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement. 15 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 16 to 19 IN0 to IN3 AI Channel 0 through Channel 3 Analog Inputs. 21 Exposed Pad NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is (EPAD) (EPAD) recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 12 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide