Datasheet AD7949-EP (Analog Devices) - 5

link to page 6 link to page 6
Enhanced Product AD7949-EP TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications −55°C to +125°C, unless otherwise noted.
Table 3. Parameter1 Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 2.2 µs Acquisition Time tACQ 1.8 µs Time Between Conversions tCYC 4.0 µs Data Write/Read During Conversion tDATA 1.0 µs CNV Pulse Width tCNVH 10 ns SCK Period tSCK tDSDO + 2 ns SCK Low Time tSCKL 11 ns SCK High Time tSCKH 11 ns SCK Falling Edge to Data Remains Valid tHSDO 4 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 2.7 V 18 ns VIO Above 2.3 V 23 ns VIO Above 1.8 V 28 ns CNV Low to SDO D15 MSB Valid tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns VIO Above 1.8 V 25 ns CNV High or Last SCK Fal ing Edge to SDO High Impedance tDIS 32 ns CNV Low to SCK Rising Edge tCLSCK 10 ns DIN Valid Setup Time from SCK Rising Edge tSDIN 5 ns DIN Valid Hold Time from SCK Rising Edge tHDIN 5 ns 1 See Figure 2 and Figure 3 for load conditions. Rev. B | Page 5 of 12 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide