Datasheet AD7606-EP (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 8-Channel DAS with 16-Bit, Bipolar, Simultaneous Sampling ADC |
| Seiten / Seite | 15 / 6 — AD7606-EP. Data Sheet. TIMING SPECIFICATIONS. Table 2. Limit at TMIN, … |
| Dateiformat / Größe | PDF / 279 Kb |
| Dokumentensprache | Englisch |
AD7606-EP. Data Sheet. TIMING SPECIFICATIONS. Table 2. Limit at TMIN, TMAX. 0.1 × VDRIVE and 0.9 × VDRIVE
Modelllinie für dieses Datenblatt
Textversion des Dokuments
AD7606-EP Data Sheet TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference and internal reference, TA = TMIN to TMAX, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Limit at TMIN, TMAX 0.1 × VDRIVE and 0.9 × VDRIVE 0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels Logic Input Levels Parameter Min Typ Max Min Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 6.65 6.65 µs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 11.1 µs Serial mode reading after a conversion; VDRIVE = 2.7 V 11.4 12.4 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV Conversion time 4.1 4.5 5 4.1 4.5 5 µs Oversampling off 9.6 11.7 9.6 11.7 µs Oversampling by 2 20.5 25 20.5 25 µs Oversampling by 4 42 52 42 52 µs Oversampling by 8 86 105 86 105 µs Oversampling by 16 173 212 173 212 µs Oversampling by 32 347 424 347 424 µs Oversampling by 64 tRESET 50 50 ns RESET high pulse width t1 40 45 ns CONVST x high to BUSY high t2 25 25 ns Minimum CONVST x low pulse t3 25 25 ns Minimum CONVST x high pulse t4 0 0 ns BUSY falling edge to CS falling edge setup time t 1 5 0.5 0.5 ms Maximum delay al owed between CONVST A, CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY fal ing edge t7 25 25 ns Minimum delay between RESET low to CONVST x high 1 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. Rev. 0 | Page 6 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference and internal reference, TA = TMIN to TMAX, unless otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
Table 2. Limit at TMIN, TMAX 0.1 × VDRIVE and 0.9 × VDRIVE 0.3 × VDRIVE and 0.7 × VDRIVE Logic Input Levels Logic Input Levels Parameter Min Typ Max Min Typ Max Unit Description
PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 6.65 6.65 µs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 11.1 µs Serial mode reading after a conversion; VDRIVE = 2.7 V 11.4 12.4 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV Conversion time 4.1 4.5 5 4.1 4.5 5 µs Oversampling off 9.6 11.7 9.6 11.7 µs Oversampling by 2 20.5 25 20.5 25 µs Oversampling by 4 42 52 42 52 µs Oversampling by 8 86 105 86 105 µs Oversampling by 16 173 212 173 212 µs Oversampling by 32 347 424 347 424 µs Oversampling by 64 tRESET 50 50 ns RESET high pulse width t1 40 45 ns CONVST x high to BUSY high t2 25 25 ns Minimum CONVST x low pulse t3 25 25 ns Minimum CONVST x high pulse t4 0 0 ns BUSY falling edge to CS falling edge setup time t 1 5 0.5 0.5 ms Maximum delay al owed between CONVST A, CONVST B rising edges t6 25 25 ns Maximum time between last CS rising edge and BUSY fal ing edge t7 25 25 ns Minimum delay between RESET low to CONVST x high 1 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. Rev. 0 | Page 6 of 15 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE