Datasheet AD7291-EP (Analog Devices) - 6

AD7291-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T E RS V N2 N1 I I N0I D/ DRI V V V P V 20 19 18 17 16 V 1 15 SCL IN3 14 V 2 SDA IN4 AD7291-EP V 3 13 AS1 IN5 TOP VIEW (Not to Scale) V 4 12 ALERT IN6 V 5 11 AS0 IN7 6 7 8 9 10 F DD RE ND ND1 CAP V G V G D NOTES 1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE SHOULD BE SOLDERED
002
TO PCB GROUND FOR PROPER HEAT DISSIPATION AND PERFORMANCE.
15915- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 to 5, VIN3, VIN4, Analog Inputs. The AD7291-EP has eight single-ended analog inputs that are multiplexed into the on-chip track- 18 to 20 VIN5, VIN6, and-hold amplifier. Each input channel can accept analog inputs from 0 V to 2.5 V. Any unused input channels VIN7, VIN0, must be connected to GND1 to avoid noise pickup. VIN1, VIN2 6 GND1 Ground. Ground reference point for the internal reference circuitry on the AD7291-EP. All analog input signals and the external reference signals must be referred to this GND1 voltage. The GND1 pin must be connected to the ground plane of a system. All ground pins must ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. The VREF pin must be decoupled to this ground pin via a 10 μF decoupling capacitor. 7 VREF Internal Reference/External Reference Supply. The nominal internal reference voltage of 2.5 V appears at this pin. Provided the output is buffered, the on-chip reference can be taken from this pin and applied externally to the rest of a system. Decoupling capacitors must be connected to this pin to decouple the reference buffer. For best performance, it is recommended to use a 10 μF decoupling capacitor on this pin to GND1. The internal reference can be disabled and an external reference supplied to this pin if required. The input voltage range for the external reference is 2.0 V to 2.5 V. 8 DCAP Decoupling Capacitor Pin. Decoupling capacitors (1 μF recommended) are connected to this pin to decouple the internal low dropout regulator (LDO). 9 GND Ground. Ground reference point for all analog and digital circuitry on the AD7291-EP. The GND pin must be con- nected to the ground plane of the system. All ground pins must ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Both DCAP and VDD pins must be decoupled to this GND pin. 10 VDD Supply Voltage, 2.8 V to 3.6 V. This supply must be decoupled to GND with 10 μF and 100 nF decoupling capacitors. 11, 13 AS0, AS1 Logic Inputs. Together, the logic state of these two inputs selects a unique I2C address for the AD7291-EP. See the AD7291 data sheet for details. The device address depends on the voltage applied to these pins. 12 ALERT Digital Output. This pin acts as an out-of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATALOW register values. See the AD7291 data sheet for further details. 14 SDA Digital Input/Output. Serial bus bidirectional data. This open-drain output requires a pull-up resistor. The output coding is straight binary for the voltage channels and twos complement for the temperature sensor result. 15 SCL Digital Inputs. Serial I2C Bus Clock. This input requires a pull-up resistor. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz operating modes. 16 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines the voltage at which the interface operates. This pin must be decoupled to GND. The voltage range on this pin is 1.65 V to 3.6 V and can be less than the voltage at VDD but must never exceed it by more than 0.3 V. 17 PD/RST Power-Down Pin. This pin places the device into a ful power-down mode and enables power conservation when operation is not required. This pin can be used to reset the device by toggling the pin low for a minimum of 1 ns and a maximum of 100 ns. If the maximum time is exceeded, the device enters power-down mode. When placing the device in full power-down mode, the analog inputs must be returned to 0 V. EPAD EPAD Exposed Pad. The exposed metal paddle on the bottom of the LFCSP package must be soldered to PCB ground for proper functionality and heat dissipation. Rev. 0 | Page 6 of 8 Document Outline FEATURES ENHANCED PRODUCT FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE