Datasheet LTC2358-16 (Analog Devices)

LTC2358-16 Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
FEATURES DESCRIPTION
n
200ksps per Channel Throughput
The LTC®2358-16 is a 16-bit, low noise 8-channel simulta- n
Eight Buffered Simultaneous Sampling Channels
neous sampling successive approximation register (SAR) n
500pA/12nA Max Input Leakage at 85°C/125°C
ADC with buffered differential, wide common mode range n
±1LSB INL (Maximum, ±10.24V Range)
picoamp inputs. Operating from a 5V low voltage supply, n
Guaranteed 16-Bit, No Missing Codes
flexible high voltage supplies, and using the internal refer- n
Differential, Wide Common Mode Range Inputs
ence and buffer, each channel of this SoftSpanTM ADC can be n
Per-Channel SoftSpan Input Ranges:
independently configured on a conversion-by-conversion
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V
basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V
5.12V signals. Individual channels may also be disabled n
94.2dB Single-Conversion SNR (Typical)
to increase throughput on the remaining channels. n
−111dB THD (Typical) at fIN = 2kHz
The integrated picoamp-input analog buffers, wide input n
128dB CMRR (Typical) at fIN = 200Hz
common mode range and 128dB CMRR of the LTC2358-16 n
Rail-to-Rail Input Overdrive Tolerance
al ow the ADC to directly digitize a variety of signals us- n Integrated Reference and Buffer (4.096V) ing minimal board space and power. This input signal n SPI CMOS (1.8V to 5V) and LVDS Serial I/O flexibility, combined with ±1LSB INL, no missing codes n Internal Conversion Clock, No Cycle Latency at 16 bits, and 94.2dB SNR, makes the LTC2358-16 an n 219mW Power Dissipation (27mW/Ch Typical) ideal choice for many high voltage applications requiring n 48-Lead (7mm x 7mm) LQFP Package wide dynamic range. The LTC2358-16 supports pin-selectable SPI CMOS (1.8V
APPLICATIONS
to 5V) and LVDS serial interfaces. Between one and eight lanes of data output may be employed in CMOS mode, n Programmable Logic Controllers allowing the user to optimize bus width and throughput. n Industrial Process Control All registered trademarks and trademarks are the property of their respective owners. Protected n Power Line Monitoring by U.S. Patents, including 7705765, 7961132, 8319673, 9197235. n Test and Measurement
TYPICAL APPLICATION
15V 5V 1.8V TO 5V 0.1µF 0.1µF 2.2µF 0.1µF
Integral Nonlinearity vs Output Code and Channel
CMOS OR LVDS I/O INTERFACE 1.00 ±10.24V RANGE FULLY BUFFERS VCC VDD VDDLBYP OVDD LVDS/CMOS TRUE BIPOLAR DRIVE (IN– = 0V) 0.75 ARBITRARY DIFFERENTIAL IN0+ PD S/H ALL CHANNELS +10V +5V IN0– 0.50 S/H LTC2358-16 0V 0V SDO0 0.25 S/H • • • –10V –5V • • • S/H 0 16-BIT MUX SDO7 TRUE BIPOLAR UNIPOLAR S/H SAR ADC SCKO –0.25 +10V +10V INL ERROR (LSB) SCKI S/H SDI –0.50 0V 0V S/H CS BUSY –0.75 –10V –10V SAMPLE IN7+ S/H CNV CLOCK IN7– VEE REFBUF REFIN GND –1.00 DIFFERENTIAL INPUTS IN+/IN– WITH –32768 –16384 0 16384 32768 WIDE INPUT COMMON MODE RANGE 235816 TA01a OUTPUT CODE EIGHT BUFFERED 47µF 0.1µF 0.1µF 235816 TA01b SIMULTANEOUS SAMPLING CHANNELS –15V Rev A Document Feedback For more information www.analog.com 1 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS REFERENCE BUFFER CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS CONFIGURATION TABLES FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS