Datasheet ADN2805 (Analog Devices)

1.25 Gbps Clock and Data Recovery IC Data Sheet ADN2805 FEATURES GENERAL DESCRIPTION Locks to 1.25 Gbps NRZ serial data input
The ADN2805 provides the receiver functions of quantization
Patented clock recovery architecture
and clock and data recovery for 1.25 Gbps. The ADN2805
No reference clock required
automatically locks to all data rates without the need for an
Loss-of-lock indicator
external reference clock or programming. All SONET jitter
I2C interface to access optional features
requirements are met, including jitter transfer, jitter generation,
Single-supply operation: 3.3 V
and jitter tolerance.
Low power: 390 mW typical
All specifications are specified for −40°C to +85°C ambient
5 mm × 5 mm 32-lead LFCSP, Pb free
temperature, unless otherwise noted. The ADN2805 is available
APPLICATIONS
in a compact 5 mm × 5 mm 32-lead LFCSP.
GbE line card FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL CF1 CF2 VCC VEE FREQUENCY LOOP DETECT FILTER PIN PHASE PHASE LOOP NIN BUFFER VCO SHIFTER DETECT FILTER VREF DATA RE-TIMING 2 2 ADN2805
01
DATAOUTP/ CLKOUTP/
0 1-
DATAOUTN CLKOUTN
12 07 Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE