Datasheet MAX1661, MAX1662, MAX1663 (Maxim) - 6

Serial-to-Parallel/Parallel-to-Serial Converters and Load-Switch Controllers with SMBus Interface _______________Detailed Description Table 1. SMBus Addresses
The MAX1661/MAX1662/MAX1663 convert 2-wire
ADD MAX1661 MAX1662 MAX1663
SMBus serial data into three latched parallel outputs GND 0100000 0100001 0100010 (I/O1, I/O2, I/O3). These devices are intended to drive N- channel and P-channel, high-side MOSFET switches in High-Z 0111100 0111101 0111110 load power-management systems. Readback capabili- (floating) ties allow them to function as parallel-to-serial devices. VCC 1001000 1001001 1001010 The MAX1661/MAX1662/MAX1663 operate from a single supply with a typical quiescent current of 3µA, making
SMBus Send-Byte Commands
them ideal for portable applications (Figure 1). If the MAX1661/MAX1662/MAX1663 receives its correct slave address (Table 1) followed by R/W low, it expects
SMBus Interface Operation
to receive a byte of information. If the device detects a The SMBus serial interface is a 2-wire interface with start or stop condition prior to clocking in the byte of multi-mastering capability. From a software perspec- data, it considers this an error condition and disregards tive, the MAX1661/MAX1662/MAX1663 appears as a all of the data. set of byte-wide registers that contain information con- The MAX1661/MAX1662/MAX1663 generates a first trolling the I/O_ pins, masking capabilities, and a con- acknowledge after the write bit and another acknowledge trol bit that determines which register is being after the data. It executes the data byte at the rising edge addressed. The 2-wire slave interface employs stan- of SMBCLK following the second acknowledge, just prior dard SMBus send-byte and receive-byte protocols. to the stop condition (Figure 2a). See Table 2 for send- SMBDATA and SMBCLK are Schmitt-triggered inputs byte operations. that can accommodate slower edges; however, the ris- ing and falling edges should still be faster than 1µs and SMBSUS
(Suspend-Mode) Input
300ns, respectively. Except for the stop and start con- The SMBus can write to either of the normal-data and ditions, the SMBDATA input never transitions while suspend-mode registers via the MSB (bit 7) of the SMBCLK is high. A third interface line (SMBSUS) is send-byte word (Table 2). The state of the SMBSUS used to execute commands asynchronously from previ- input selects which register contents (normal data or ously stored registers (see the section SMBSUS suspend mode) are applied to the I/O_ pins. Driving
MAX1661/MAX1662/MAX1663
(Suspend-Mode) Input). This reduces the inherent SMBSUS low selects the suspend-mode register, while delay in a standard 2-wire serial interface. In the driving SMBSUS high selects the normal-data register. receive-byte operation, the SMBus interface reads This feature allows the system to select between two back I/O states and thermal-shutdown status. different power-plane configurations asynchronously, eliminating latencies introduced by the serial bus.
SMBus Addressing
SMBSUS typically connects to the SUSTAT# signal in a Each slave device only responds to two addresses: its notebook computer. own unique address and the alert response address. The device’s unique address is determined at power-up
SMBus Receive-Byte Operation
(Table 1). The three-level state of the address-select pin If the MAX1661/MAX1662/MAX1663 receives its correct (ADD) is only sampled upon power-on reset (POR) caus- slave address, followed by R/W high, the device ing momentary input bias current of 100µA. The address becomes a slave transmitter (Figure 2b). After receiving will not change until the part is power cycled. Stray the address data, the device generates an acknowl- capacitance in excess of 50pF on the ADD pin when edge during the acknowledge clock pulse and drives floating may cause address recognition problems. SMBDATA in sync with SMBCLK. The SMB protocol The normal start condition consists of a high-to-low requires that the master terminate the read transmis- transition on SMBDATA while SMBCLK is high. After the sion by not acknowledging during the acknowledge bit start condition, the master transmits a 7-bit address fol- of SMBCLK. See Table 3 for receive-byte data format. lowed by a single bit to determine whether the device is Figure 4 shows the complete receive-byte operation sending or receiving (high = READ, low = WRITE). If timing diagram. the address is correct, the MAX1661/MAX1662/ The logic states of the three I/O pins can be read over MAX1663 sends an acknowledgment pulse by pulling the serial interface (Table 3). The state of the I/O pins is SMBDATA low. Otherwise, the address is not recog- sampled at the falling edge of the SMBCLK pulse that nized and the device stays off the bus and waits until follows the R/W bit and acknowledge bit (Figure 4). The another start condition occurs. states of the I/O bits in the status register reflect the
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