Datasheet ADuM4121/ADuM4121-1 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | High Voltage, Isolated Gate Driver with Internal Miller Clamp, 2 A Output |
| Seiten / Seite | 16 / 1 — High Voltage, Isolated Gate Driver with. Internal Mil er Clamp, 2 A … |
| Dateiformat / Größe | PDF / 535 Kb |
| Dokumentensprache | Englisch |
High Voltage, Isolated Gate Driver with. Internal Mil er Clamp, 2 A Output. Data Sheet. ADuM4121/. ADuM4121-1. FEATURES
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High Voltage, Isolated Gate Driver with Internal Mil er Clamp, 2 A Output Data Sheet ADuM4121/ ADuM4121-1 FEATURES GENERAL DESCRIPTION 2 A peak output current (<2 Ω RDSON)
The ADuM4121/ADuM4121-11 are 2 A isolated, single-channel
2.5 V to 6.5 V input
drivers that employ Analog Devices, Inc.’s iCoupler® technology
4.5 V to 35 V output
to provide precision isolation. The ADuM4121/ADuM4121-1
Undervoltage lockout (UVLO) at 2.5 V VDD1
provide 5 kV rms isolation in the wide-body, 8-lead SOIC package.
Multiple UVLO options on VDD2
Combining high speed CMOS and monolithic transformer
Grade A: 4.4 V (typical) UVLO on VDD2
technology, these isolation components provide outstanding
Grade B: 7.3 V (typical) UVLO on VDD2
performance characteristics superior to alternatives such as the
Grade C: 11.3 V (typical) UVLO on VDD2
combination of pulse transformers and gate drivers.
Precise timing characteristics
The ADuM4121/ADuM4121-1 operate with an input supply
53 ns maximum isolator and driver propagation delay
ranging from 2.5 V to 6.5 V, providing compatibility with lower
CMOS input logic levels
voltage systems. In comparison to gate drivers that employ high
High common-mode transient immunity: >150 kV/µs
voltage level translation methodologies, the ADuM4121/
High junction temperature operation: 125°C
ADuM4121-1 offer the benefit of true, galvanic isolation
Default low output
between the input and the output.
Internal Miller clamp Safety and regulatory approvals ( pending)
The ADuM4121/ADuM4121-1 include an internal Mil er clamp
UL recognition per UL 1577
that activates at 2 V on the fal ing edge of the gate drive output,
5 kV rms for 1-minute withstand
supplying the driven gate with a lower impedance path to reduce
CSA Component Acceptance Notice 5A
the chance of Miller capacitance induced turn on.
VDE certificate of conformity (pending)
Options exists to al ow the thermal shutdown to be enabled or
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
disabled. As a result, the ADuM4121/ADuM4121-1 provide
VIORM = 849 V peak
reliable control over the switching characteristics of insulated
Wide-body, 8-lead SOIC
gate bipolar transistor (IGBT)/metal oxide semiconductor field,
APPLICATIONS
effect transistor (MOSFET) configurations over a wide range of switching voltages.
Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters Gallium nitride (GaN)/silicon carbide (SiC) power devices FUNCTIONAL BLOCK DIAGRAM ADuM4121/ UVLO TSD VDD1 1 8 VDD2 ADuM4121-1 DECODE 2 ENCODE AND V 7 V I+ LOGIC OUT VI– 3 6 CLAMP 2V GND1 4 5 GND UVLO 2
001 14967- Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS REGULATORY INFORMATION PACKAGE CHARACTERISTICS INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT VI+ and VI− Operation PROPAGATION DELAY-RELATED PARAMETERS UNDERVOLTAGE LOCKOUT (UVLO) OUTPUT LOAD CHARACTERISTICS Miller Clamp POWER DISSIPATION INSULATION LIFETIME TYPICAL APPLICATIONS OUTLINE DIMENSIONS ORDERING GUIDE
The ADuM4121/ADuM4121-11 are 2 A isolated, single-channel
2.5 V to 6.5 V input
drivers that employ Analog Devices, Inc.’s iCoupler® technology
4.5 V to 35 V output
to provide precision isolation. The ADuM4121/ADuM4121-1
Undervoltage lockout (UVLO) at 2.5 V VDD1
provide 5 kV rms isolation in the wide-body, 8-lead SOIC package.
Multiple UVLO options on VDD2
Combining high speed CMOS and monolithic transformer
Grade A: 4.4 V (typical) UVLO on VDD2
technology, these isolation components provide outstanding
Grade B: 7.3 V (typical) UVLO on VDD2
performance characteristics superior to alternatives such as the
Grade C: 11.3 V (typical) UVLO on VDD2
combination of pulse transformers and gate drivers.
Precise timing characteristics
The ADuM4121/ADuM4121-1 operate with an input supply
53 ns maximum isolator and driver propagation delay
ranging from 2.5 V to 6.5 V, providing compatibility with lower
CMOS input logic levels
voltage systems. In comparison to gate drivers that employ high
High common-mode transient immunity: >150 kV/µs
voltage level translation methodologies, the ADuM4121/
High junction temperature operation: 125°C
ADuM4121-1 offer the benefit of true, galvanic isolation
Default low output
between the input and the output.
Internal Miller clamp Safety and regulatory approvals ( pending)
The ADuM4121/ADuM4121-1 include an internal Mil er clamp
UL recognition per UL 1577
that activates at 2 V on the fal ing edge of the gate drive output,
5 kV rms for 1-minute withstand
supplying the driven gate with a lower impedance path to reduce
CSA Component Acceptance Notice 5A
the chance of Miller capacitance induced turn on.
VDE certificate of conformity (pending)
Options exists to al ow the thermal shutdown to be enabled or
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
disabled. As a result, the ADuM4121/ADuM4121-1 provide
VIORM = 849 V peak
reliable control over the switching characteristics of insulated
Wide-body, 8-lead SOIC
gate bipolar transistor (IGBT)/metal oxide semiconductor field,
APPLICATIONS
effect transistor (MOSFET) configurations over a wide range of switching voltages.
Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters Gallium nitride (GaN)/silicon carbide (SiC) power devices FUNCTIONAL BLOCK DIAGRAM ADuM4121/ UVLO TSD VDD1 1 8 VDD2 ADuM4121-1 DECODE 2 ENCODE AND V 7 V I+ LOGIC OUT VI– 3 6 CLAMP 2V GND1 4 5 GND UVLO 2
001 14967- Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS REGULATORY INFORMATION PACKAGE CHARACTERISTICS INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PRINTED CIRCUIT BOARD (PCB) LAYOUT VI+ and VI− Operation PROPAGATION DELAY-RELATED PARAMETERS UNDERVOLTAGE LOCKOUT (UVLO) OUTPUT LOAD CHARACTERISTICS Miller Clamp POWER DISSIPATION INSULATION LIFETIME TYPICAL APPLICATIONS OUTLINE DIMENSIONS ORDERING GUIDE