Datasheet L5965 (STMicroelectronics) - 2

L5965 Overview 1 Overview
L5965 is a multichannel voltage regulator able to offer flexibility and ease to use, together with a set of features that make it compliant to car passenger applications that require a certain level of safety. The product includes input and output monitors, independent band-gaps, ground loss monitors, internal compensation networks, that also help reduce the BOM, digital and analog BIST, fault pin. In this product, there are 7 different regulators. A first battery-compatible regulator, a controller that can supply several current flow thanks to the use of external MOSs. A second regulator with integrated MOS that can be used as a pre-regulator for currents up to about 2.6 A. Two bucks, post regulators, one boost that can be used to supply, for example, a CAN bus, one LDO and a 1% accurate reference voltage for the microcontroller. All output voltages can be selected via memory cells (OTP) that can be programmed before using the PMIC. This guarantees precision and safety, since output voltages are not susceptible to variations due to the external environment. It also contributes to reducing the number of external components. Through the OTP it is also possible to decide the switching frequency of some regulators, the current limitation, select the main buck and the system power-on sequence. Programming can also be done at customer’s production line. There is also an SPI bus, used to program the PMIC and to communicate with the microcontroller. Through this bus it is possible to set overvoltage and undervoltage thresholds, enable the spread spectrum, select the soft start time and many other things. The SPI is also used to communicate the status of the bucks in case of fault, over- temperature or other events. The maximum free run switching frequency of the bucks is 2.4 MHz, modifiable through external synchronization signals. The PMIC can manage watchdog and reset signals.
1.1 Simplified block diagram Figure 1. Simplified block diagram
VBAT INDEPENDENT SUPPLIES Pre-BUCK1 Buck pre/post regulator compatible to battery V WKUP Voltage controller references 5-3.8-3.3-1.8-1.2-1.1-1.0-0.8 V @ 0.4 MHz Safety Pre-BUCK2 Buck pre/post regulator compatible to battery V FAULT management 5.0-3.6-3.3-1.5-1.35-1.2-1.1-1.0 V @ 1.35-2.6 A ● 0.4-2.4 MHz BUCK3 Buck post regulator compatible to 5.5 V max Watchdog & RESETB Internal Reset 3.3-2.5-2.3-2.0-1.8-1.35-1.2-1.0 V @ 1.4 A ● 2.4 MHz compensation BUCK4 Buck post regulator compatible to 5.5 V max SPI SPI Internal 3.3-1.8-1.35-1.3-1.25-1.2-1.12-1.1 V @ 1 A ● 2.4 MHz compensation OTP BOOST Boost post regulator compatible to 5.5 V max 7 V @ 0.2 A, 5 V @ 0.3 A ● 2.4 MHz Supervisors Diagnostics LDO Linear post regulator compatible to 5.5 V max 5-3.3-2.8-2.5-1.8-1.3-1.25-1.2 V @ 300-600 mA Supervisors SYNC_IN Oscillator SYNC_OUT VREF Internally connected to the battery Supervisors 4.1 - 3.3 - 2.5 - 1.8 V @ 20 mA Note: Buck min peak currents. GAPG1005181515PS
DS12567
-
Rev 2 page 2/85
Document Outline 1 Overview 1.1 Simplified block diagram 1.2 Functional block diagram 2 Pins description 3 Electrical specifications 3.1 Absolute maximum ratings & operating voltage 3.2 Thermal data 3.2.1 Thermal resistance 3.2.2 Thermal warning and protection 3.3 Electrical characteristics 3.3.1 Electrical characteristic curves 4 Functional description 4.1 Programming by OTP 4.2 Voltage regulators and features description 4.2.1 VREG 4.2.2 Pre regulator BUCK1 4.2.3 Pre regulator BUCK2 4.2.4 Post regulator BUCK3 4.2.5 Post regulator BUCK4 4.2.6 BOOST 4.2.7 LDO 4.2.8 VREF 4.2.9 ADC 4.2.10 Wake up pin (WKUP) 4.2.11 Synchronizing pin (SYNC in/out) 4.2.12 Reset and Fault 4.2.13 Configurable watchdog and reset 4.2.14 Under-Voltage, Over-Voltage and Power-Good 4.2.15 Temperature control and VBATx voltage through internal ADC 4.2.16 Maximum Duty Cycle and Refresh Mode for Buck 4.2.17 Frequency-Hopping Spread Spectrum 5 SPI format and register mapping 5.1 SPI frame CRC generator 5.2 SPI registers mapping 5.2.1 SPI REG BUCK1 5.2.2 SPI REG BUCK2 5.2.3 SPI REG WD_REC_EN 5.2.4 SPI REG BUCK4 5.2.5 SPI REG BOOST VREF 5.2.6 SPI REG BUCK EN 5.2.7 SPI REG WD 5.2.8 SPI REG BUCK STAT1 5.2.9 SPI REG BUCK STAT2 5.2.10 SPI REG Fault Table PWUP 5.2.11 SPI REG ADC TH1 5.2.12 SPI REG ADC TH2 5.2.13 SPI REG ADC TH3 5.2.14 SPI REG ADC TH4 5.2.15 SPI REG ADC TH5 5.2.16 SPI REG ADC TH6 5.2.17 SPI REG ADC TH7 5.2.18 SPI REG ADC VBAT1 5.2.19 SPI REG ADC VBAT2 5.2.20 SPI REG OT Warning 5.2.21 SPI Fault STAT 5.2.22 SPI Silicon Version 5.2.23 SPI Device Identification 6 Device operating mode 6.1 Shutdown mode 6.2 Standby mode 6.3 INIT mode 6.4 REC mode 6.5 RAMPUP MAIN and SEC_UP 6.6 ACTIVE mode 6.7 OTP program mode 6.8 OTP bit mapping and register configuration 6.9 OTP (SAF) registers 6.9.1 SAF_REG_OP 6.9.2 SAF_REG_CFG 6.9.3 SAF_REG_DI 6.9.4 SAF_REG_D0_Bit_Ts 6.9.5 SAF_REG_STAT 6.10 Power down phase 6.11 Power up programming 7 Functional safety requirements 7.1 Functions and safety mechanism related to safety requirements 7.2 System safety mechanism 8 Application information 8.1 External components calculation 8.1.1 BUCK1 controller 8.1.1.1 RSENSE 8.1.1.2 BUCK1 output inductor 8.1.1.3 BUCK1 output capacitor 8.1.1.4 BUCK1 bootstrap capacitor 8.1.1.5 BUCK1 compensation network 8.1.2 BUCK2 controller 8.1.2.1 BUCK2 output inductor 8.1.2.2 BUCK2 output capacitor 8.1.2.3 BUCK2 compensation network 8.1.3 BUCK3, BUCK4 8.1.3.1 Output inductor and capacitor 8.1.3.2 Bootstrap capacitor for BUCK3 and BUCK4 8.1.3.3 Input capacitor 8.1.4 BOOST 8.1.4.1 BOOST output inductor 8.1.4.2 BOOST output capacitor 8.1.4.3 BOOST compensation network 8.1.4.4 Output diode for the BOOST converter 8.1.4.5 Input capacitor selection 8.2 PCB Layout example (BUCK1 as main regulator) 9 Package information 9.1 VFQFPN-48 (7x7x1.0 mm - opt. D) package information 9.2 VFQFPN-48 (7x7x1.0) marking information Revision history