Preliminary Datasheet CXT-741Gxx (Cissoid) - 8
Hersteller | Cissoid |
Beschreibung | High Temperature Automotive Configurable Logic Gates |
Seiten / Seite | 12 / 8 — May. 19. High Temperature Automotive Configurable Logic Gates. … |
Revision | 1.0 |
Dateiformat / Größe | PDF / 332 Kb |
Dokumentensprache | Englisch |
May. 19. High Temperature Automotive Configurable Logic Gates. Preliminary Datasheet. CXT-741G175 Timing Characteristics
Modelllinie für dieses Datenblatt
Textversion des Dokuments
Contact : Gonzalo Picún (+32-10-489214)
May. 19 High Temperature Automotive Configurable Logic Gates Preliminary Datasheet CXT-741G175 Timing Characteristics Bold underlined
values indicate values over the whole temperature range (-55°C < TJ < +175°C); All typical values are at TA=25°C
Symbol Parameter Test conditions VDD Min. Typ Max. Units
CL=30pF RL=1KΩ 1.65V -1.95V
20
CL=30pF RL=500Ω 2.25V - 2.75V
35
f MHz MAX Maximum Frequency CL=50pF RL=500Ω 3V - 3.6V
50
CL=50pF RL=500Ω 4.5V - 5.5V
70
1.65V -1.95V
2
CLK Minimum 2.25V - 2.75V
2
t ns WCLK Pulse Width 3V - 3.6V
2
4.5V - 5.5V
1
1.65V -1.95V
3
CLRB Minimum 2.25V - 2.75V
2
t ns WCLRB Pulse Width 3V - 3.6V
2
4.5V - 5.5V
2
CL=30pF RL=1KΩ 1.65V -1.95V
27.43
CL=30pF Propagation delay RL=500Ω 2.25V - 2.75V
16
tPD from CLK positive ns CL=50pF edge to output RL=500Ω 3V - 3.6V
12.98
CL=50pF RL=500Ω 4.5V - 5.5V
8.96
CL=30pF RL=1KΩ 1.65V -1.95V
24.33
CL=30pF Propagation delay RL=500Ω 2.25V - 2.75V
13.65
t from CLRB negative ns PCLRB CL=50pF edge to output RL=500Ω 3V - 3.6V
10.91
CL=50pF RL=500Ω 4.5V - 5.5V
7.8
1.65V -1.95V
2
2.25V - 2.75V
1
t ns SU Setup time 3V - 3.6V
1
4.5V - 5.5V
1
1.65V -1.95V
1
2.25V - 2.75V
1
th Hold time ns 3V - 3.6V
1
4.5V - 5.5V
1 PUBLIC Doc. PDS-192011 V1.0 WWW.CISSOID.COM
8 of 12