Datasheet UT69RH051 (Aeroflex) - 5
| Hersteller | Aeroflex |
| Beschreibung | Radiation-Hardened MicroController |
| Seiten / Seite | 20 / 5 — 8 BYTES. INDIRECT. ACCESS. ONLY. SCRATCH. PAD AREA. DIRECT OR. BIT. … |
| Dateiformat / Größe | PDF / 1.0 Mb |
| Dokumentensprache | Englisch |
8 BYTES. INDIRECT. ACCESS. ONLY. SCRATCH. PAD AREA. DIRECT OR. BIT. ADDRESSABLE. SEGMENT. REGISTER. BANKS
Modelllinie für dieses Datenblatt
- 5962F9563801QQA 5962F9563801QQC 5962F9563801QQX 5962F9563801QYA 5962F9563801QYC 5962F9563801QYX 5962F9563801VQA 5962F9563801VQC 5962F9563801VQX 5962F9563801VYA 5962F9563801VYC 5962F9563801VYX 5962G9563801QQA 5962G9563801QQC 5962G9563801QQX 5962G9563801QYA 5962G9563801QYC 5962G9563801QYX 5962G9563801VQA 5962G9563801VQC 5962G9563801VQX 5962G9563801VYA 5962G9563801VYC 5962G9563801VYX 5962H9563801QQA 5962H9563801QQC 5962H9563801QQX 5962H9563801QYA 5962H9563801QYC 5962H9563801QYX 5962H9563801VQA 5962H9563801VQC 5962H9563801VQX 5962H9563801VYA 5962H9563801VYC 5962H9563801VYX 5962R9563801QQA 5962R9563801QQC 5962R9563801QQX 5962R9563801QYA 5962R9563801QYC 5962R9563801QYX 5962R9563801VQA 5962R9563801VQC 5962R9563801VQX 5962R9563801VYA 5962R9563801VYC 5962R9563801VYX UT69RH051P-CA UT69RH051P-CC UT69RH051P-CX UT69RH051W-PA UT69RH051W-PC UT69RH051W-PX
Textversion des Dokuments
8 BYTES F8 FF F0 F7 INDIRECT
• •
ACCESS
• •
ONLY
• •
88 8F SCRATCH 80 87 PAD AREA 78 7F 70 77
• • • • • •
38 3F DIRECT OR 30 37 INDIRECT 28 2F ACCESS BIT ADDRESSABLE 20 27 SEGMENT 18 1F 10 17 REGISTER BANKS 08 0F 00 07 Figure 3. Internal Data Memory Organization 2.1.3 Reset
While RST is high, PSEN and the port pins are pulled high; ALE The reset input is the RST pin. To reset, hold the RST pin high is pulled low. All SFRs are reset to their reset values as shown for a minimum of 24 oscillator periods while the oscillator is in table 3. The internal Data Memory content is indeterminate. running. The CPU generates an internal reset from the external signal. The port pins are driven to the reset state as soon as a valid The processor will begin operation one machine cycle after the high is detected on the RST pin. RST line is brought low. A memory access occurs immediately after the RST line is brought low, but the data is not brought into the processor. The memory access repeats on the next machine cycle and actual processing begins at that time. 5
• •
ACCESS
• •
ONLY
• •
88 8F SCRATCH 80 87 PAD AREA 78 7F 70 77
• • • • • •
38 3F DIRECT OR 30 37 INDIRECT 28 2F ACCESS BIT ADDRESSABLE 20 27 SEGMENT 18 1F 10 17 REGISTER BANKS 08 0F 00 07 Figure 3. Internal Data Memory Organization 2.1.3 Reset
While RST is high, PSEN and the port pins are pulled high; ALE The reset input is the RST pin. To reset, hold the RST pin high is pulled low. All SFRs are reset to their reset values as shown for a minimum of 24 oscillator periods while the oscillator is in table 3. The internal Data Memory content is indeterminate. running. The CPU generates an internal reset from the external signal. The port pins are driven to the reset state as soon as a valid The processor will begin operation one machine cycle after the high is detected on the RST pin. RST line is brought low. A memory access occurs immediately after the RST line is brought low, but the data is not brought into the processor. The memory access repeats on the next machine cycle and actual processing begins at that time. 5