Datasheet Si8941/46/47 (Silicon Labs) - 6
| Hersteller | Silicon Labs |
| Beschreibung | Isolated Delta-Sigma Modulator for Current Shunt Measurement |
| Seiten / Seite | 35 / 6 — 3. Current Sense Application. Figure 3.1. Current Sense Application. … |
| Revision | 0.5 |
| Dateiformat / Größe | PDF / 542 Kb |
| Dokumentensprache | Englisch |
3. Current Sense Application. Figure 3.1. Current Sense Application. silabs.com
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Si8941/46/47 Data Sheet Current Sense Application
3. Current Sense Application
In the driver circuit presented below, the Si8941/46/47 is used to amplify the voltage across the sense resistor, RSENSE, where it is oversampled and converted into a 1-bit bitstream, then transmitted across the isolation barrier to be processed by the system controller/ FPGA. Placing the sense resistor before the load is known as high-side sensing and isolation is needed because the voltage of RSENSE with respect to ground will swing between 0 V and the high voltage rail connected to the drain of Q1. Floating Low Side High Voltage Gate Driver Gate Driver 3 to 5.5V Bus 24V Supply Supply Supply VDDA PWM Q1 C5 VOA 0.1uF GNDA VDDI GNDI DISABLE R6 VDDB DT VOB GNDB VDDI R3 Si8234 Q3 1.82K C3 D1 C2 C4 FPGA 0.1uF 5.6V 0.1uF Gate 0.1uF 1 8 Driver VDDA VDDB RSENSE PID R1 20 2 7 AIP ACLK Control 3 6 SINC3 C1 AIN ADAT 10nF 4 5 GNDA GNDB R2 20 Load Clock Si894x Q2
Figure 3.1. Current Sense Application
The load in this application can be a motor winding or a similar inductive winding. In a three-phase motor drive application, this circuit would be repeated three times, one for each phase. RSENSE should be a small resistor value to reduce power loss. However, an ex- cessively low resistance will reduce the signal-to-noise ratio of the measurement. Si8941/46/47 offers two specified linear full-scale in- put options, ±62.5 mV (Si8941A/46A/47A) and ±250 mV (Si8941B/46B/47B), for optimizing the value of RSENSE. Further product or- dering options include whether the CLK pin is an input (Si8941) or an output (Si8946/47). AIP and AIN connections to the RSENSE resistor should be made as close as possible to each end of the RSENSE resistor as trace resistance will add error to the measurement. The input to the Si8941/46/47 is differential, and the PCB traces back to the input pins should run in parallel. This ensures that any large noise transients that occur on the high-voltage side are coupled equally to the AIP and AIN pins and will be rejected by the Si8941/46/47 as a common-mode signal. The Si8941/46/47 has intrinsic low-pass filtering at approximately 800 kHz. If further input filtering is required, a passive, differential RC low-pass filter can be placed between RSENSE and the input pins. Values of R1 = R2 = 20 Ω and C1 = 10 nF provides a cutoff at approximately 400 kHz. For the lowest gain error, R1 and R2 should always be less than 33 Ω to keep the source impedance sufficient- ly low compared to the Si8941/46/47 input impedance. The common-mode voltage of AIN and AIP must be greater than –0.2 V but less than 1 V with respect to GNDA. To meet this require- ment, route a trace from the GNDA pin of the Si8941/46/47 to one side of the RSENSE resistor. In this circuit, GNDA, RSENSE, the source of Q1, and the drain of Q2 are connected. The ground of the gate driver (one half of the Silicon Labs’ Si8234 in this example) is also commonly connected to the same node. The Q1 gate driver has a floating supply of 24 V. Since the input and output of the Si8941/46/47 are galvanically isolated from each other, separate power supplies are necessary on each side. Q3, R3, C3, and D1 make a regulator circuit for powering the input side of the Si8941/46/47 from this floating supply. D1 establishes a voltage of 5.6 V at the base of Q3. R3 is selected to provide a Zener cur- rent of 10 mA for D1. C3 provides filtering at the base of Q3, and the emitter output of Q3 provides approximately 5 V to VDDA. C2 is a bypass capacitor for the supply and should be placed at the VDDA pin with its return trace connecting to the GNDA connection at RSENSE. C4, the local bypass capacitor for the B-side of Si8941/46/47, should be placed closed to VDDB supply pin with its return close to GNDB. The output signal typically goes directly to a digital filter for additional processing. The digital filter may be implemented by a dedicated FPGA in the system or may be a peripheral in the main system controller. The Si8941 expects an external clock to provide
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| Building a more connected world. Preliminary Rev. 0.5 | 6 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
3. Current Sense Application
In the driver circuit presented below, the Si8941/46/47 is used to amplify the voltage across the sense resistor, RSENSE, where it is oversampled and converted into a 1-bit bitstream, then transmitted across the isolation barrier to be processed by the system controller/ FPGA. Placing the sense resistor before the load is known as high-side sensing and isolation is needed because the voltage of RSENSE with respect to ground will swing between 0 V and the high voltage rail connected to the drain of Q1. Floating Low Side High Voltage Gate Driver Gate Driver 3 to 5.5V Bus 24V Supply Supply Supply VDDA PWM Q1 C5 VOA 0.1uF GNDA VDDI GNDI DISABLE R6 VDDB DT VOB GNDB VDDI R3 Si8234 Q3 1.82K C3 D1 C2 C4 FPGA 0.1uF 5.6V 0.1uF Gate 0.1uF 1 8 Driver VDDA VDDB RSENSE PID R1 20 2 7 AIP ACLK Control 3 6 SINC3 C1 AIN ADAT 10nF 4 5 GNDA GNDB R2 20 Load Clock Si894x Q2
Figure 3.1. Current Sense Application
The load in this application can be a motor winding or a similar inductive winding. In a three-phase motor drive application, this circuit would be repeated three times, one for each phase. RSENSE should be a small resistor value to reduce power loss. However, an ex- cessively low resistance will reduce the signal-to-noise ratio of the measurement. Si8941/46/47 offers two specified linear full-scale in- put options, ±62.5 mV (Si8941A/46A/47A) and ±250 mV (Si8941B/46B/47B), for optimizing the value of RSENSE. Further product or- dering options include whether the CLK pin is an input (Si8941) or an output (Si8946/47). AIP and AIN connections to the RSENSE resistor should be made as close as possible to each end of the RSENSE resistor as trace resistance will add error to the measurement. The input to the Si8941/46/47 is differential, and the PCB traces back to the input pins should run in parallel. This ensures that any large noise transients that occur on the high-voltage side are coupled equally to the AIP and AIN pins and will be rejected by the Si8941/46/47 as a common-mode signal. The Si8941/46/47 has intrinsic low-pass filtering at approximately 800 kHz. If further input filtering is required, a passive, differential RC low-pass filter can be placed between RSENSE and the input pins. Values of R1 = R2 = 20 Ω and C1 = 10 nF provides a cutoff at approximately 400 kHz. For the lowest gain error, R1 and R2 should always be less than 33 Ω to keep the source impedance sufficient- ly low compared to the Si8941/46/47 input impedance. The common-mode voltage of AIN and AIP must be greater than –0.2 V but less than 1 V with respect to GNDA. To meet this require- ment, route a trace from the GNDA pin of the Si8941/46/47 to one side of the RSENSE resistor. In this circuit, GNDA, RSENSE, the source of Q1, and the drain of Q2 are connected. The ground of the gate driver (one half of the Silicon Labs’ Si8234 in this example) is also commonly connected to the same node. The Q1 gate driver has a floating supply of 24 V. Since the input and output of the Si8941/46/47 are galvanically isolated from each other, separate power supplies are necessary on each side. Q3, R3, C3, and D1 make a regulator circuit for powering the input side of the Si8941/46/47 from this floating supply. D1 establishes a voltage of 5.6 V at the base of Q3. R3 is selected to provide a Zener cur- rent of 10 mA for D1. C3 provides filtering at the base of Q3, and the emitter output of Q3 provides approximately 5 V to VDDA. C2 is a bypass capacitor for the supply and should be placed at the VDDA pin with its return trace connecting to the GNDA connection at RSENSE. C4, the local bypass capacitor for the B-side of Si8941/46/47, should be placed closed to VDDB supply pin with its return close to GNDB. The output signal typically goes directly to a digital filter for additional processing. The digital filter may be implemented by a dedicated FPGA in the system or may be a peripheral in the main system controller. The Si8941 expects an external clock to provide
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 6 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History