Datasheet Si8941/46/47 (Silicon Labs) - 4
| Hersteller | Silicon Labs |
| Beschreibung | Isolated Delta-Sigma Modulator for Current Shunt Measurement |
| Seiten / Seite | 35 / 4 — 2. System Overview. Si894x. Transmitter. Receiver. Figure 2.1. Functional … |
| Revision | 0.5 |
| Dateiformat / Größe | PDF / 542 Kb |
| Dokumentensprache | Englisch |
2. System Overview. Si894x. Transmitter. Receiver. Figure 2.1. Functional Block Diagram. silabs.com
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Si8941/46/47 Data Sheet System Overview
2. System Overview
The input to the Si8941/46/47 is designed for low-voltage, differential signals. This is ideal for connection to low-resistance current shunt measurement resistors. The Si8941A/46A/47A has a specified full scale input range of ±62.5 mV, and the Si8941B/46B/47B has a specified full scale input range of ±250 mV. This allows the user to choose low-ohmic resistance value sense resistors to minimize system power loss. The analog input stage of the Si8941/46/47 is a fully differential amplifier feeding the input of a second-order, delta-sigma (ΔΣ) modula- tor that digitizes the input signal into a 1-bit output stream. The isolated data output ADAT pin of the converter provides a stream of digital ones and zeros that is synchronous to the ACLK pin. The Si8946/47 clock is generated internally while the Si8941 clock is provi- ded externally. The time average of this serial bit-stream output is proportional to the analog input voltage. The Si8941/46/47 implements a fail-safe output when the high-side supply voltage VDDA goes away. The fail-safe output is a steady- state logic 0 on ADAT for the externally clocked Si8941. The fail-safe output is a steady state logic 1 on ADAT for the internally clocked Si8946/47. The clock output ACLK of the Si8946/47 will stop after 256 cycles with a steady state logic 1. When the supply comes back, the clock will be turned back on and the normal DSM data stream will be output in approximately 250 μs. To differentiate from the fail- safe output, a full-scale input signal will generate a single one or zero every 128 bits at ADAT, depending on the actual polarity of the signal being sensed. When a loss of VDDA supply occurs, the part will automatically move into a lower power mode that reduces IDDB current to approxi- mately 1 mA. Similarly, a loss of VDDB supply will reduce IDDA current to approximately 1 mA. When the supply voltage is returned, normal operation begins in approximately 250 μs.
Si894x
VDDA VDDB AIP CLK ACLK DSM AIN ADAT
Transmitter Receiver
GNDA CMOS Isolation GNDB
Figure 2.1. Functional Block Diagram silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 4 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
2. System Overview
The input to the Si8941/46/47 is designed for low-voltage, differential signals. This is ideal for connection to low-resistance current shunt measurement resistors. The Si8941A/46A/47A has a specified full scale input range of ±62.5 mV, and the Si8941B/46B/47B has a specified full scale input range of ±250 mV. This allows the user to choose low-ohmic resistance value sense resistors to minimize system power loss. The analog input stage of the Si8941/46/47 is a fully differential amplifier feeding the input of a second-order, delta-sigma (ΔΣ) modula- tor that digitizes the input signal into a 1-bit output stream. The isolated data output ADAT pin of the converter provides a stream of digital ones and zeros that is synchronous to the ACLK pin. The Si8946/47 clock is generated internally while the Si8941 clock is provi- ded externally. The time average of this serial bit-stream output is proportional to the analog input voltage. The Si8941/46/47 implements a fail-safe output when the high-side supply voltage VDDA goes away. The fail-safe output is a steady- state logic 0 on ADAT for the externally clocked Si8941. The fail-safe output is a steady state logic 1 on ADAT for the internally clocked Si8946/47. The clock output ACLK of the Si8946/47 will stop after 256 cycles with a steady state logic 1. When the supply comes back, the clock will be turned back on and the normal DSM data stream will be output in approximately 250 μs. To differentiate from the fail- safe output, a full-scale input signal will generate a single one or zero every 128 bits at ADAT, depending on the actual polarity of the signal being sensed. When a loss of VDDA supply occurs, the part will automatically move into a lower power mode that reduces IDDB current to approxi- mately 1 mA. Similarly, a loss of VDDB supply will reduce IDDA current to approximately 1 mA. When the supply voltage is returned, normal operation begins in approximately 250 μs.
Si894x
VDDA VDDB AIP CLK ACLK DSM AIN ADAT
Transmitter Receiver
GNDA CMOS Isolation GNDB
Figure 2.1. Functional Block Diagram silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 4 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History