Datasheet ADSP-21261, ADSP-21262, ADSP-21266 (Analog Devices) - 7

link to page 7 link to page 7
ADSP-21261 /ADSP-21262 /ADSP-21266 Serial Peripheral (Compatible) Interface
the JTAG or test access port, will be assigned to each customer. The device will ignore a wrong key. Emulation features and The serial peripheral interface is an industry-standard synchro- external boot modes are only available after the correct key is nous serial link, enabling the ADSP-2126x SPI-compatible port scanned. to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and
Program Booting
one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can The internal memory of the ADSP-2126x boots at system operate in a multimaster environment by interfacing with up to power-up from an 8-bit EPROM via the parallel port, an SPI four other SPI-compatible devices, either acting as a master or master, an SPI slave, or an internal boot. Booting is determined slave device. The ADSP-2126x SPI-compatible peripheral by the boot configuration (BOOT_CFG1–0) pins. implementation also features programmable baud rates at up to
Phase-Locked Loop
50 MHz for a core clock of 200 MHz and up to 37.5 MHz for a core clock of 150 MHz, clock phases, and polarities. The The ADSP-2126x uses an on-chip phase-locked loop (PLL) to ADSP-2126x SPI-compatible port uses open-drain drivers to generate the internal clock for the core. On power-up, the support a multimaster configuration and to avoid data CLK_CFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1. contention. After booting, numerous other ratios can be selected via soft- ware control. The ratios are made up of software configurable
Parallel Port
numerator values from 1 to 64 and software configurable divi- The parallel port provides interfaces to SRAM and peripheral sor values of 2, 4, 8, and 16. devices. The multiplexed address and data pins (AD15–0) can
Power Supplies
access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16- The ADSP-2126x has separate power supply connections for the bit, the maximum data transfer rate is one-third the core clock internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) speed. As an example, a clock rate of 200 MHz is equivalent to power supplies. The internal and analog supplies must meet the 66M byte/sec, and a clock rate of 150 MHz is equivalent to 1.2 V requirement. The external supply must meet the 3.3 V 50M byte/sec. requirement. All external supply pins must be connected to the same power supply. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the paral- Note that the analog supply pin (AVDD) powers the lel port register read/write functions. The RD, WR, and ALE ADSP-2126x’s internal clock generator PLL. To produce a stable (address latch enable) pins are the control pins for the clock, it is recommended that PCB designs use an external filter parallel port. circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see
Timers
Figure 2. (A recommended ferrite chip is the muRata The ADSP-2126x has a total of four timers: a core timer able to BLM18AG102SN1D). To reduce noise coupling, the PCB generate periodic software interrupts, and three general-pur- should use a parallel pair of power and ground planes for pose timers that can generate periodic interrupts and be VDDINT and GND. Use wide traces to connect the bypass capac- independently set to operate in one of three modes: itors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 2 are inputs to • Pulse waveform generation mode the processor and not the analog ground plane on the board— • Pulse width count/capture mode the AVSS pin should connect directly to digital ground (GND) at the chip. • External event watchdog mode The core timer can be configured to use FLAG3 as a timer expired output signal, and each general-purpose timer has one
ADSP-212xx 100nF 10nF 1nF
bidirectional pin and four registers that implement its mode of
V A DDINT VDD
operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables all three
HIGH-Z FERRITE BEAD CHIP A
general-purpose timers independently.
VSS ROM-Based Security LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS
The ADSP-2126x has a ROM security feature that provides hardware support for securing user software code by preventing Figure 2. Analog Power Filter Circuit unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any exter- nal code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through Rev. G | Page 7 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide