Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 8

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ADSP-21371/ ADSP-21375
SHARC processor are 48 bits wide, instruction throughput point of the PWM period. In this mode, it is possible to produce when executing code from external SDRAM memory is 2 asymmetrical PWM patterns that produce lower harmonic dis- instructions every 3 SDCLK (peripheral) clock cycles over a 32- tortion in three-phase PWM inverters. bit wide external port, and 2 instructions every 6 SDCLK clock cycles over a 16-bit external port. Non SDRAM external mem-
Digital Applications Interface (DAI)
ory address space is shown in Table 6. The digital applications interface (DAI) provides the ability to connect various peripherals to any of the processor’s DAI pins
Table 6. External Memory for Non SDRAM Addresses
(DAI_P1 to DAI_P20). Programs make these connections using the signal routing unit
Bank Size in Words Address Range
(SRU), shown in Figure 1. Bank 0 14M 0x0020 0000–0x00FF FFFF The SRU is a matrix routing unit (or group of multiplexers) that Bank 1 16M 0x0400 0000–0x04FF FFFF enables the peripherals provided by the DAI to be intercon- Bank 2 16M 0x0800 0000–0x08FF FFFF nected under software control. This allows easy use of the DAI Bank 3 16M 0x0C00 0000–0x0CFF FFFF associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon-
External Port Throughput
figurable signal paths. The throughput for the external port, based on 133 MHz clock In the ADSP-21371, the DAI includes eight serial ports, four and 32-bit data bus, is 177M bytes/s for the AMI and 532M precision clock generators (PCG), and an input data port (IDP). bytes/s for SDRAM. For the ADSP-21375, the DAI includes four serial ports, four precision clock generators (PCG) and an input data port (IDP).
Asynchronous Memory Controller
The IDP provides an additional input path to the core of the The asynchronous memory controller provides a configurable processor, configurable as either eight channels of I2S serial interface for up to four separate banks of memory or I/O data, or a single 20-bit wide synchronous parallel data acquisi- devices. Each bank can be independently programmed with dif- tion port. Each data channel has its own DMA channel that is ferent timing parameters, enabling connection to a wide variety independent from the processor’s serial ports. of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory con-
Serial Ports
trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2, The processors feature eight synchronous serial ports on the and 3 occupy a 16M word window in the processor’s address ADSP-21371 and four on the ADSP-21375. The SPORTs pro- space but, if not fully populated, these windows are not made vide an inexpensive interface to a wide variety of digital and contiguous by the memory controller logic. The banks can also mixed-signal peripheral devices such as Analog Devices’ be configured as 8-bit or 16-bit wide buses for ease of interfac- AD183x family of audio codecs, ADCs, and DACs. The serial ing to a range of memories and I/O devices tailored either to ports are made up of two data lines, a clock, and frame sync. The high performance or to low cost and power. data lines can be programmed to either transmit or receive and
Pulse-Width Modulation
each data line has a dedicated DMA channel. The PWM module is a flexible, programmable, PWM waveform For the ADSP-21371, serial ports are enabled via 16 program- generator that can be programmed to generate the required mable pins and simultaneous receive or transmit pins that switching patterns for various applications related to motor and support up to 32 transmit or 32 receive channels of audio data engine control or audio power control. The PWM generator can when all eight SPORTs are enabled, or eight duplex TDM generate either center-aligned or edge-aligned PWM wave- streams of 128 channels per frame. forms. In addition, it can generate complementary signals on For the ADSP-21375, serial ports are enabled via eight program- two outputs in paired mode or independent signals in non- mable pins and simultaneous receive or transmit pins that paired mode (applicable to a single group of four PWM support up to 16 transmit or 16 receive channels of audio data waveforms). when all four SPORTs are enabled, or four duplex TDM streams The entire PWM module has four groups of four PWM outputs of 128 channels per frame. each. Therefore, this module generates 16 PWM outputs in The serial ports operate at a maximum data rate of fPCLK/4. total. Each PWM group produces two pairs of PWM signals on Serial port data can be automatically transferred to and from the four PWM outputs. on-chip memory via dedicated DMA channels. Each of the The PWM generator is capable of operating in two distinct serial ports can work in conjunction with another serial port to modes while generating center-aligned PWM waveforms: single provide TDM support. One SPORT provides two transmit sig- update mode or double update mode. In single update mode the nals while the other SPORT provides the two receive signals. duty cycle values are programmable only once per PWM period. The frame sync and clock are shared. This results in PWM patterns that are symmetrical about the mid-point of the PWM period. In double update mode, a sec- ond updating of the PWM registers is implemented at the mid- Rev. D | Page 8 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide