Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 5

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ADSP-21371 /ADSP-21375 Data Register File
processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow Each processing element contains a general-purpose data regis- the creation of up to 32 circular buffers (16 primary register sets, ter file. The register files transfer data between the computation 16 secondary). The DAGs automatically handle address pointer units and the data buses, and store intermediate results. These wraparound, reduce overhead, increase performance, and sim- 10-port, 32-register (16 primary, 16 secondary) register files, plify implementation. Circular buffers can start and end at any combined with the SHARC’s enhanced Harvard architecture, memory location. allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as
Flexible Instruction Set
R0–R15 and in PEY as S0–S15. The 48-bit instruction word accommodates a variety of parallel
Context Switch
operations, for concise programming. For example, the proces- sors can conditionally execute a multiply, an add, and a subtract Many of the processor’s registers have secondary registers that in both processing elements while branching and fetching up to can be activated during interrupt servicing for a fast context four 32-bit values from memory—all in a single instruction. switch. The data registers in the register file, the DAG registers, and the multiplier result register all have secondary registers.
On-Chip Memory
The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. The ADSP-21371 processor contains 1 megabit of internal RAM and four megabits of internal mask-programmable ROM (see
Universal Registers
Table 3 on Page 6) and the ADSP-21375 processor contains 0.5 megabits of internal RAM and two megabits of internal mask- Universal registers can be used for general purpose tasks. The programmable ROM (see Table 4 on Page 7). Each block can be USTAT (4) registers allow easy bit manipulations (Set, Clear, configured for different combinations of code and data storage. Toggle, Test, XOR) for all system registers (control/status) of Each memory block supports single-cycle, independent accesses the core. by the core processor and I/O processor. The processor’s mem- The data bus exchange register PX permits data to be passed ory architecture, in combination with its separate on-chip buses, between the 64-bit PM data bus and the 64-bit DM data bus, or allow two data transfers from the core and one from the I/O between the 40-bit register file and the PM data bus. These reg- processor, in a single cycle. isters contain hardware to handle the data width difference. The ADSP-21371 processor’s SRAM can be configured as a
Timer
maximum of 32k words of 32-bit data, 64k words of 16-bit data, 21.3k words of 48-bit instructions (or 40-bit data), or combina- The processors contain a core timer that can generate periodic tions of different word sizes up to 1 megabit. All of the memory software interrupts. The core timer can be configured to use can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16- FLAG3 as a timer expired signal. bit floating-point storage format is supported that effectively
Single-Cycle Fetch of an Instruction and Four Operands
doubles the amount of data that may be stored on-chip. Conver- sion between the 32-bit floating-point and 16-bit floating-point The processors feature an enhanced Harvard architecture in formats is performed in a single instruction. While each mem- which the data memory (DM) bus transfers data and the pro- ory block can store combinations of code and data, accesses are gram memory (PM) bus transfers both instructions and data most efficient when one block stores data using the DM bus for (see Figure 2). With the processor’s separate program and data transfers, and the other block stores instructions and data using memory buses and on-chip instruction cache, the processor can the PM bus for transfers. simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data
Instruction Cache
transfers. In this case, the instruction must be available in The processors include an on-chip instruction cache that the cache. enables three-bus operation for fetching an instruction and four
On-Chip Memory Bandwidth
data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This The internal memory architecture allows four accesses at the cache allows full speed execution of core, looped operations same time to any of the four blocks, assuming no block con- such as digital filter multiply-accumulates, and FFT butterfly flicts. The total bandwidth is gained with DMD and PMD buses processing. (2  64-bits, core CLK) and the IOD0/1 buses (2  32-bit, PCLK).
Data Address Generators with Zero-Overhead Hardware Circular Buffer Support ROM-Based Security
The processors’s two data address generators (DAGs) are used The processors have a ROM security feature that provides hard- for indirect addressing and implementing circular data buffers ware support for securing user software code by preventing in hardware. Circular buffers allow efficient programming of unauthorized reading from the internal code when enabled. delay lines and other data structures required in digital signal When using this feature, the processor does not boot-load any Rev. D | Page 5 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide