Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 4

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ADSP-21371/ ADSP-21375 SHARC FAMILY CORE ARCHITECTURE
Entering SIMD mode also has an effect on the way data is trans- ferred between memory and the processing elements. When in The ADSP-21371/ADSP-21375 processors are code compatible SIMD mode, twice the data bandwidth is required to sustain at the assembly level with the ADSP-2136x, ADSP-2126x, computational operation in the processing elements. Because of ADSP-21160x, and ADSP-21161N, and with the first generation this requirement, entering SIMD mode also doubles the band- ADSP-2106x SHARC processors. The ADSP-21371/ width between memory and the processing elements. When ADSP-21375 processors share architectural features with the using the DAGs to transfer data in SIMD mode, two data values ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC are transferred with each access of memory or the register file. processors, as shown in Figure 2 and detailed in the following sections.
Independent, Parallel Computation Units SIMD Computational Engine
Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit The processors contain two computational processing elements (ALU), multiplier, and shifter. These units perform all opera- that operate as a single-instruction, multiple-data (SIMD) tions in a single cycle. The three units within each processing engine. The processing elements are referred to as PEX and element are arranged in parallel, maximizing computational PEY, and each contains an ALU, multiplier, shifter, and register throughput. Single multifunction instructions execute parallel file. PEX is always active, and PEY may be enabled by setting the ALU and multiplier operations. In SIMD mode, the parallel PEYEN mode bit in the MODE1 register. When this mode is ALU and multiplier operations occur in both processing ele- enabled, the same instruction is executed in both processing ele- ments. These computation units support IEEE 32-bit single- ments, but each processing element operates on different data. precision floating-point, 40-bit extended precision floating- This architecture is efficient at executing math intensive DSP point, and 32-bit fixed-point data formats. algorithms. S
JTAG FLAG TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 DAG2 16x32 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX DM DATA 64 64-BIT RF DATA RF SWAP MULTIPLIER SHIFTER ALU Rx/Fx Sx/SFx ALU SHIFTER MULTIPLIER PEx PEy 16x40-BIT 16x40-BIT MRF MRB MSB MSF 80-BIT 80-BIT ASTATx ASTATy 80-BIT 80-BIT STYKx STYKy
Figure 2. SHARC Core Block Diagram Rev. D | Page 4 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide