Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | SHARC Processor |
| Seiten / Seite | 56 / 2 — ADSP-21371/. ADSP-21375. TABLE OF CONTENTS. REVISION HISTORY. 4/13—Rev. C … |
| Revision | D |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
ADSP-21371/. ADSP-21375. TABLE OF CONTENTS. REVISION HISTORY. 4/13—Rev. C to Rev. D
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ADSP-21371/ ADSP-21375 TABLE OF CONTENTS
Summary ... 1 Package Information .. 18 Dedicated Audio Components ... 1 Maximum Power Dissipation ... 18 General Description ... 3 Absolute Maximum Ratings ... 18 SHARC Family Core Architecture .. 4 ESD Sensitivity ... 18 Family Peripheral Architecture .. 6 Timing Specifications ... 18 I/O Processor Features ... 10 Output Drive Currents ... 49 System Design .. 10 Test Conditions .. 49 Development Tools ... 11 Capacitive Loading .. 49 Additional Information .. 12 Thermal Characteristics .. 50 Related Signal Chains .. 12 208-Lead LQFP_EP Pinout ... 51 Pin Function Descriptions ... 13 Package Dimensions ... 55 ADSP-21371/ADSP-21375 Specifications .. 16 Automotive Products .. 56 Operating Conditions .. 16 Ordering Guide ... 56 Electrical Characteristics ... 17
REVISION HISTORY 4/13—Rev. C to Rev. D
Added 1.0 V, 200 MHz specifications to the following timing Corrected Extended Precision Normal or Instruction Word specifications. (48 bits) ADSP-21375 Internal Memory Space ...7 Clock Input ..21 Updated Development Tools ... 11 Precision Clock Generator (Direct Pin Routing) ...26 Added section Related Signal Chains ...12 SDRAM Interface Timing ..28 Revised MS1-0 pin description in Memory Read—Bus Master ...29 Pin Function Descriptions .. 13 Memory Write—Bus Master ..31 Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in Serial Ports ..33 Pin Function Descriptions .. 13 Input Data Port (IDP) ..38 Corrected TJUNCTION specifications in Operating Conditions .. 16 S/PDIF Transmitter Input Data Timing ..42 Added footnote 3 to Table 25 in S/PDIF Receiver ..43 Memory Read—Bus Master ... 29 SPI Interface—Slave ...45 Updated Serial Ports timing parameter data in Serial Ports— External Clock ... 33 Updated Serial Ports timing parameter data in Serial Ports— Internal Clock .. 34 Changed Max values in Table 33 in Pulse-Width Modulation Generators (PWM) ... 40 Updated timing parameters in Table 37 and in Figure 31 in SPI Interface—Master .. 44 Rev. D | Page 2 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide
ADSP-21371/ ADSP-21375 TABLE OF CONTENTS
Summary ... 1 Package Information .. 18 Dedicated Audio Components ... 1 Maximum Power Dissipation ... 18 General Description ... 3 Absolute Maximum Ratings ... 18 SHARC Family Core Architecture .. 4 ESD Sensitivity ... 18 Family Peripheral Architecture .. 6 Timing Specifications ... 18 I/O Processor Features ... 10 Output Drive Currents ... 49 System Design .. 10 Test Conditions .. 49 Development Tools ... 11 Capacitive Loading .. 49 Additional Information .. 12 Thermal Characteristics .. 50 Related Signal Chains .. 12 208-Lead LQFP_EP Pinout ... 51 Pin Function Descriptions ... 13 Package Dimensions ... 55 ADSP-21371/ADSP-21375 Specifications .. 16 Automotive Products .. 56 Operating Conditions .. 16 Ordering Guide ... 56 Electrical Characteristics ... 17
REVISION HISTORY 4/13—Rev. C to Rev. D
Added 1.0 V, 200 MHz specifications to the following timing Corrected Extended Precision Normal or Instruction Word specifications. (48 bits) ADSP-21375 Internal Memory Space ...7 Clock Input ..21 Updated Development Tools ... 11 Precision Clock Generator (Direct Pin Routing) ...26 Added section Related Signal Chains ...12 SDRAM Interface Timing ..28 Revised MS1-0 pin description in Memory Read—Bus Master ...29 Pin Function Descriptions .. 13 Memory Write—Bus Master ..31 Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in Serial Ports ..33 Pin Function Descriptions .. 13 Input Data Port (IDP) ..38 Corrected TJUNCTION specifications in Operating Conditions .. 16 S/PDIF Transmitter Input Data Timing ..42 Added footnote 3 to Table 25 in S/PDIF Receiver ..43 Memory Read—Bus Master ... 29 SPI Interface—Slave ...45 Updated Serial Ports timing parameter data in Serial Ports— External Clock ... 33 Updated Serial Ports timing parameter data in Serial Ports— Internal Clock .. 34 Changed Max values in Table 33 in Pulse-Width Modulation Generators (PWM) ... 40 Updated timing parameters in Table 37 and in Figure 31 in SPI Interface—Master .. 44 Rev. D | Page 2 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide