Datasheet ADSP-21467, ADSP-21469 (Analog Devices) - 7

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ADSP-21467 /ADSP-21469 FAMILY PERIPHERAL ARCHITECTURE VISA and ISA Access to External Memory
The processors contain a rich set of peripherals that support a The DDR2 controller also supports VISA code operation which wide variety of applications including high quality audio, medi- reduces the memory load since the VISA instructions are com- cal imaging, communications, military, test equipment, 3D pressed. Moreover, bus fetching is reduced because, in the best graphics, speech recognition, motor control, imaging, and other case, one 48-bit fetch contains three valid instructions. Code applications. execution from the traditional ISA operation is also supported. Note that code execution is only supported from bank 0 regard-
External Port
less of VISA/ISA. Table 5 shows the address ranges for The external port interface supports access to the external mem- instruction fetch in each mode. ory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be pro-
Table 5. External Bank 0 Instruction Fetch
grammed as either asynchronous or synchronous memory. The
Access Type Size in Words Address Range
external ports are comprised of the following modules. ISA (NW) 4M 0x0020 0000 – 0x005F FFFF • An Asynchronous Memory Interface which communicates VISA (SW) 10M 0x0060 0000 – 0x00FF FFFF with SRAM, Flash, and other devices that meet the stan- dard asynchronous SRAM access protocol. The AMI
Shared External Memory
supports 2M words of external memory in bank 0 and 4M words of external memory in bank 1, bank 2, and bank 3. The processors support connection to common shared external • A DDR2 DRAM controller. External memory devices up to DDR2 memory with other ADSP-2146x processors to create 2 Gbits in size can be supported. shared external bus processor systems. This support includes: • Arbitration logic to coordinate core and DMA transfers • Distributed, on-chip arbitration for the shared external bus between internal and external memory over the external • Fixed and rotating priority bus arbitration port. • Bus time-out logic
External Memory
• Bus lock The external port on the processors provide a high perfor- Multiple processors can share the external bus with no addi- mance, glueless interface to a wide variety of industry-standard tional arbitration logic. Arbitration logic is included on-chip to memory devices. The external port may be used to interface to allow the connection of up to two processors. Table 10 on synchronous and/or asynchronous memory devices through the Page 14 provides descriptions of the pins used in multiprocessor use of its separate internal DDR2 memory controller. The 16-bit systems. DDR2 DRAM controller connects to industry-standard syn- chronous DRAM devices, while the second 8-bit asynchronous
DDR2 Support
memory controller is intended to interface to a variety of mem- The processors support a 16-bit DDR2 interface operating at a ory devices. Four memory select pins enable up to four separate maximum frequency of half the core clock. Execution from devices to coexist, supporting any desired combination of syn- external memory is supported. External memory devices up to chronous and asynchronous device types. Non-DDR2 DRAM 2 Gbits in size can be supported. external memory address space is shown in Table 4.
DDR2 DRAM Controller Table 4. External Memory for Non-DDR2 DRAM Addresses
The DDR2 DRAM controller provides a 16-bit interface to up to four separate banks of industry-standard DDR2 DRAM devices.
Bank Size in Words Address Range
Fully compliant with the DDR2 DRAM standard, each bank can Bank 0 2M 0x0020 0000 – 0x003F FFFF have its own memory select line (DDR2_CS3 – DDR2_CS0), Bank 1 4M 0x0400 0000 – 0x043F FFFF and can be configured to contain between 32 Mbytes and Bank 2 4M 0x0800 0000 – 0x083F FFFF 256 Mbytes of memory. DDR2 DRAM external memory address space is shown in Table 6. Bank 3 4M 0x0C00 0000 – 0x0C3F FFFF A set of programmable timing parameters is available to config-
SIMD Access to External Memory
ure the DDR2 DRAM banks to support memory devices. The DDR2 controller supports SIMD access on the 64-bit EPD
Table 6. External Memory for DDR2 DRAM Addresses
(external port data bus) which allows to access the complemen- tary registers on the PEy unit in the normal word space (NW).
Bank Size in Words Address Range
This improves performance since there is no need to explicitly Bank 0 62M 0x0020 0000 – 0x03FF FFFF load the complimentary registers as in SISD mode. Bank 1 64M 0x0400 0000 – 0x07FF FFFF Bank 2 64M 0x0800 0000 – 0x0BFF FFFF Bank 3 64M 0x0C00 0000 – 0x0FFF FFFF Rev. B | Page 7 of 76 | March 2013 Document Outline Summary Table Of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth Nonsecured ROM ROM-Based Security Digital Transmission Content Protection Family Peripheral Architecture External Port External Memory SIMD Access to External Memory VISA and ISA Access to External Memory Shared External Memory DDR2 Support DDR2 DRAM Controller Asynchronous Memory Controller External Port Throughput Link Ports MediaLB Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral Interface UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA IIR Accelerator FFT Accelerator FIR Accelerator System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing AMI Read AMI Write Shared Memory Bus Request Link Ports Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation (PWM) Generators S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Test Conditions Output Drive Currents Capacitive Loading Thermal Characteristics Thermal Diode CSP_BGA Ball Assignment—Automotive Models CSP_BGA Ball Assignment—Standard Models Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide