Datasheet ADSP-21477, ADSP-21478, ADSP-21479 (Analog Devices) - 6

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ADSP-21477/ ADSP-21478/ ADSP-21479
bits within the 48-bit instruction to create more efficient and floating-point storage format is supported that effectively dou- compact code. The program sequencer supports fetching these bles the amount of data that may be stored on-chip. Conversion 16-bit and 32-bit instructions from both internal and external between the 32-bit floating-point and 16-bit floating-point SDRAM memory. This support is not extended to the asynchro- formats is performed in a single instruction. While each mem- nous memory interface (AMI). Source modules need to be built ory block can store combinations of code and data, accesses are using the VISA option, in order to allow code generation tools most efficient when one block stores data using the DM bus for to create these more efficient opcodes. transfers, and the other block stores instructions and data using the PM bus for transfers.
On-Chip Memory
Using the DM bus and PM buses, with one bus dedicated to a The processors contain varying amounts of internal RAM and memory block, assures single-cycle execution with two data internal ROM which is shown in Table 3 through Table 5. Each transfers. In this case, the instruction must be available in the block can be configured for different combinations of code and cache. data storage. Each memory block supports single-cycle, inde- pendent accesses by the core processor and I/O processor. The memory maps in Table 3 through Table 5 display the inter- nal memory address space of the processors. The 48-bit space The processor’s SRAM can be configured as a maximum of section describes what this address range looks like to an 160k words of 32-bit data, 320k words of 16-bit data, 106.7k instruction that retrieves 48-bit memory. The 32-bit section words of 48-bit instructions (or 40-bit data), or combinations of describes what this address range looks like to an instruction different word sizes up to 5M bits. All of the memory can be that retrieves 32-bit memory. accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
Table 3. ADSP-21477 Internal Memory Space (2M bits) IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 0x0008 0000–0x0008 FFFF 0x0010 0000–0x0011 FFFF Reserved Reserved Reserved Reserved 0x0004 8000–0x0004 8FFF 0x0008 AAAA–0x0008 BFFF 0x0009 0000–0x0009 1FFF 0x0012 0000–0x0012 FFFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 9000–0x0004 BFFF 0x0008 C000–0x0008 FFFF 0x0009 2000–0x0009 7FFF 0x0012 4000–0x0012 FFFF Reserved Reserved Reserved Reserved 0x0004 C000–0x0004 FFFF 0x0009 000–0x0009 5554 0x0009 8000–0x0009 FFFF 0x0013 0000–0x0013 FFFF Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF 0x000A 0000–0x000A AAA9 0x000A 0000–0x000AFFFF 0x0014 0000–0x0015 FFFF Reserved Reserved Reserved Reserved 0x0005 8000–0x0005 8FFF 0x000A AAAA–0x000A BFFF 0x000B 0000–0x000B 1FFF 0x0016 0000–0x0016 3FFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0005 9000–0x0005 BFFF 0x000A C000–0x000A FFFF 0x000B 2000–0x000B 7FFF 0x0016 4000–0x0016 FFFF Reserved Reserved Reserved Reserved 0x0005 C000–0x0005 FFFF 0x000B 0000–0x000B 5554 0x000B 8000–0x000B FFFF 0x0017 0000–0x0017 FFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0x0006 0000–0x0006 0FFF 0x000C 0000–0x000C 1554 0x000C 0000–0x000C 1FFF 0x0018 0000–0x0018 3FFF Reserved Reserved Reserved Reserved 0x0006 1000– 0x0006 FFFF 0x000C 1555–0x000D 5554 0x000C 2000–0x000D FFFF 0x0018 4000–0x001B FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000–0x0007 0FFF 0x000E 0000–0x000E 1554 0x000E 0000–0x000E 1FFF 0x001C 0000–0x001C 3FFF Reserved Reserved Reserved Reserved 0x0007 1000–0x0007 FFFF 0x000E 1555–0x000F 5554 0x000E 2000–0x000F FFFF 0x001C 4000–0x001F FFFF Rev. D | Page 6 of 76 | April 2017 Document Outline SHARC Processor Summary Revision History Product Application Restriction General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory On-Chip Memory Bandwidth ROM Based Security Digital Transmission Content Protection Family Peripheral Architecture External Memory External Port SIMD Access to External Memory VISA and ISA Access to External Memory SDRAM Controller Asynchronous Memory Controller External Port Throughput MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Pulse-Width Modulation Timers 2-Wire Interface Port (TWI) Shift Register I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer (WDT) Real-Time Clock System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Maximum Power Dissipation Package Information ESD Sensitivity Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Shift Register Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-LFCSP_VQ Lead Assignment 100-LQFP_EP Lead Assignment 196-BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide