Datasheet ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573, ADSP-21571, ADSP-21573 (Analog Devices)

SHARC+ Dual-Core DSP with ARM Cortex-A5 ADSP-SC570 /SC571 /SC572 /SC573 /ADSP-21571/ 21573 SYSTEM FEATURES 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Dual-enhanced SHARC+ high performance floating-point cores Low system power across automotive temperature range Up to 500 MHz per SHARC+ core MEMORY Up to 3 Mb (384 kB) L1 SRAM memory per core with parity Large on-chip L2 SRAM with ECC protection, up to 1 MB (optional ability to configure as cache) One L3 interface optimized for low system power, providing 32-bit, 40-bit, and 64-bit floating-point support 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L 32-bit fixed point devices), DDR2, or LPDDR1 SDRAM devices Byte, short word, word, long word addressed ADDITIONAL FEATURES ARM Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle Security and Protection 32 kB L1 instruction cache with parity/32 kB L1 data cache Cryptographic hardware accelerators with parity Fast secure boot with IP protection 256 kB L2 cache with parity Support for ARM TrustZone Powerful DMA system Accelerators On-chip memory protection FIR, IIR offload engines Integrated safety features Qualified for automotive applications CORE 0 CORE 1 CORE 2 SYSTEM CONTROL PERIPHERALS SIGNAL ROUTING UNIT (SRU) SECURITY AND PROTECTION SYSTEM PROTECTION (SPU)
S S
2× PRECISION CLOCK GENERATORS 1x DAI 20 SYSTEM MEMORY ASRC FULL SPORT 1x PIN PROTECTION UNIT (SMPU) 4× PAIRS 0-3 BUFFER L1 CACHE (PARITY) FAULT MANAGEMENT 32 kB L1 I-CACHE 1× S/PDIF Rx/Tx L1 SRAM (PARITY) L1 SRAM (PARITY) ARM® TrustZone® SECURITY 32 kB L1 D-CACHE 3 Mb (384 kB) 3 Mb (384 kB) 3× I2C DUAL CRC L2 CACHE SRAM/CACHE SRAM/CACHE 6 256 kB (PARITY) 2× LINK PORTS WATCHDOGS 2× SPI + 1× QUAD SPI OTP MEMORY 3× UARTs THERMAL MONITOR UNIT (TMU) 1× EPPI PROGRAM FLOW SYSTEM CROSSBAR AND DMA SUBSYSTEM 8× TIMERS + 1× COUNTER G SYS EVENT CORE 0 (GIC) P ADC CONTROL MODULE I SYS EVENT CORES 1-2 (SEC) (ACM) O 92–64 TRIGGER ROUTING (TRU) 2× CAN2.0 L3 MEMORY SYSTEM SYSTEM SD/SDIO/eMMC CLOCK, RESET, AND POWER INTERFACE L2 MEMORY ACCELERATION MLB 3-PIN CLOCK GENERATION (CGU) DDR3 DSP FUNCTIONS 1× EMAC SRAM CLOCK DISTRIBUTION DDR2 (FIR, IIR) (ECC) UNIT (CDU) LPDDR1 8x SHARC® FLAGS 8 Mb (1 MB) 7 ENCRYPTION/DECRYPTION RESET CONTROL (RCU) 1 USB 2.0 HS POWER MANAGEMENT (DPM) 16 MLB 6-PIN 6 DATA HADC (8 CHAN, 12-BIT) DEBUG UNIT 8–4 ARM® CoreSightTM WATCHPOINTS (SWU)
Figure 1. Processor Block Diagram SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Document Outline System Features Memory Additional Features Table Of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC57x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC57x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features ARM TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Parity Protected ARM L1 Cache Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Port (LP) ADC Control Module (ACM) Interface Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages (BSPs) for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 176-Lead LQFP Signal Descriptions GPIO Multiplexing for 176-Lead LQFP Package ADSP-SC57x/ADSP-2157x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAI0 Pin to DAI0 Pin Direct Routing Up/Down Counter/Rotary Encoder Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) 10/100 EMAC Timing 10/100/1000 EMAC Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 176-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide