Datasheet HMC988LP3E (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | Programmable Clock Divider & Delay, DC - 4 GHz |
| Seiten / Seite | 22 / 1 — HMC988LP3E. PROGRAMMABLE CLOCK DIVIDER AND DELAY. DC - 4 GHz. Typical … |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
HMC988LP3E. PROGRAMMABLE CLOCK DIVIDER AND DELAY. DC - 4 GHz. Typical Applications. Features. Functional Diagram
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HMC988LP3E
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Typical Applications Features
DC - 4 GHz t the HMC988lP3E is ideal for: M • basestation Digital Pre-Distortion Paths(DPD) -170 dbc/Hz floor @ 100 MHz output s • High Performance Automated test -164 dbc/Hz floor @ 2 GHz output Equipment(AtE) integrated Jitter 35 fs @ 100 MHz output rMs n - • backplane clock skew management 13 fs (calculated) @ 2 GHz output rMs io • Phase Coherence of multiple clock paths Adjustable output phase with soft/hard reset sync t • Clock Delay management to improve setup & Adjustable output delay in 60 steps of 20 ps u hold time margins Flexible input interface: ib • PCb signal flight time offset circuits lVPECl,lVDs,CMl,CMos Compatible r t • track and hold circuits for ADC/DACs AC or DC Coupling on - Chip termination 50 Ω (100 Ω Differential) is output Driver (lVPECl): k D
Functional Diagram
800 mVpp lVPECl into 50 Ω single-Ended (+3 dbm Fo) C up to 8 addressable dividers per sPi bus lo 3.3 V operation or 5 V operation with optional on- C chip regulator for best performance 3 x 3 QFn leadless sMt Package
General Description
the HMC988lP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. it is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm sMt QFn package, the clock divider offers a high level of functionality. the device works with 3.3 V supply or may be connected to 5 V supply and utilize the optional on-chip regulator. this on-chip regulator may be bypassed. up to 8 addressable HMC988lP3E devices can be used together on the sPi bus. the HMC988lP3E is ideal y suited for data converter applications with extremely low phase noise requirements. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
1
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D
v04.1014
PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Typical Applications Features
DC - 4 GHz t the HMC988lP3E is ideal for: M • basestation Digital Pre-Distortion Paths(DPD) -170 dbc/Hz floor @ 100 MHz output s • High Performance Automated test -164 dbc/Hz floor @ 2 GHz output Equipment(AtE) integrated Jitter 35 fs @ 100 MHz output rMs n - • backplane clock skew management 13 fs (calculated) @ 2 GHz output rMs io • Phase Coherence of multiple clock paths Adjustable output phase with soft/hard reset sync t • Clock Delay management to improve setup & Adjustable output delay in 60 steps of 20 ps u hold time margins Flexible input interface: ib • PCb signal flight time offset circuits lVPECl,lVDs,CMl,CMos Compatible r t • track and hold circuits for ADC/DACs AC or DC Coupling on - Chip termination 50 Ω (100 Ω Differential) is output Driver (lVPECl): k D
Functional Diagram
800 mVpp lVPECl into 50 Ω single-Ended (+3 dbm Fo) C up to 8 addressable dividers per sPi bus lo 3.3 V operation or 5 V operation with optional on- C chip regulator for best performance 3 x 3 QFn leadless sMt Package
General Description
the HMC988lP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. it is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm sMt QFn package, the clock divider offers a high level of functionality. the device works with 3.3 V supply or may be connected to 5 V supply and utilize the optional on-chip regulator. this on-chip regulator may be bypassed. up to 8 addressable HMC988lP3E devices can be used together on the sPi bus. the HMC988lP3E is ideal y suited for data converter applications with extremely low phase noise requirements. Inf F or o m r p atio r n ifc ur e n , d ishe e d lbiv y e A r n y a alog n D d t evic o p es is la beclie o eved rd to ebre sa: H ccur iattti e tae M nd re ilicarbloew . H a o ve C wever, o n rp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
1
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. www.analog.com Application Support: Pho Trademarks and registered trademarks are the property of their respective owners. ne: 978-250-33 A 4 p 3 o plica r a tio p n S p u s p @ po h rt itt : P ite ho . n c e o : 1m -800-ANALOG-D