Datasheet LT1175 (Analog Devices) - 10

LT1175
APPLICATIONS INFORMATION
normally a good thing when the regulator is used by itself, yet allows the power transistor to approach its theoretical but it prevents the user from shutting down the regulator saturation limit. when a second power source is connected to the LT1175 output. If active output pull-down is needed in shutdown,
Output Capacitor
it can be added externally with a depletion mode PFET as Several new regulator design techniques are used to make shown in Figure 2. Note that the maximum pinch-off volt- the LT1175 extremely tolerant of output capacitor selection. age of the PFET must be less than the positive logic high Like most low dropout designs which use a collector or level to ensure that the device is completely off when the drain of the power transistor to drive the output node, the regulator is active. The Motorola J177 device has 300Ω LT1175 uses the output capacitor as part of the overall on resistance for zero gate source voltage. loop compensation. Older regulators generally required the output capacitor to have a minimum value of 1μF to 3V TO 5V 100μF, a maximum ESR (Effective Series Resistance) of 0.1Ω to 1Ω and a minimum ESR in the range of 0.03Ω to 0.3Ω. These restrictions usually could be met only with s good quality solid tantalum capacitors. Aluminum capaci- + Q1* tors have problems with high ESR unless much higher d SHDN GND C values of capacitance are used (physically large). The ESR OUT ≥ 0.1μF –VIN VIN SENSE of ceramic or fi lm capacitors was too low, which made LT1175-5 ILIM2 the capacitance/ESR zero frequency too high to maintain ILIM4 OUTPUT phase margin in the regulator. Even with optimum capaci- tors, loop phase margin was very low in previous designs * MOTOROLA J177 when output current was low. These problems led to a new PINCH-OFF VOLTAGE MUST BE LESS THAN 1175 F02 POSITIVE LOGIC HIGH VOLTAGE design technique for the LT1175 error amplifi er and internal frequency compensation as shown in Figure 3.
Figure 2. Active Output Pull-Down During Shutdown
A conventional regulator loop consists of error amplifi er
Minimum Dropout Voltage
A1, driver transistor Q2 and power transistor Q1. Added Dropout voltage is the minimum voltage required between to this basic loop are secondary loops generated by Q3 input and output to maintain proper output regulation. and CF. A DC negative feedback current fed into the error For older 3-terminal regulator designs, dropout voltage amplifi er through Q3 and RN causes overall loop current was typically 1.5V to 3V. The LT1175 uses a saturating gain to be very low at light load currents. This is not a power transistor design which gives much lower dropout problem because very little gain is needed at light loads. voltage, typically 100mV at light loads and 450mV at full In addition to low gain, the parasitic pole frequency at Q2 load. Special precautions were taken to ensure that this base is extended by the DC feedback. The combination of technique does not cause quiescent supply current to be these two effects dramatically improves loop phase margin high under light load conditions. When the regulator input at light loads and makes the loop tolerant of large ESR in voltage is too low to maintain a regulated output, the pass the output capacitor. With heavy loads, loop phase and gain transistor is driven hard by the error amplifi er as it tries are not nearly as troublesome and large negative feedback to maintain regulation. The current drawn by the driver could degrade regulation. The logarithmic behavior of the transistor could be tens of milliamperes even with little or base emitter voltage of Q1 reduces Q3 negative feedback no load on the output. This indeed was the case for older at heavy loads to prevent poor regulation. IC designs that did not actively limit driver current when In a conventional design, even with the nonlinear feedback, the power transistor saturated. The LT1175 uses a new poor loop phase margin would occur at medium to heavy antisaturation technique that prevents high driver current, loads if the ESR of the output capacitor fell below 0.3Ω. 1175ff 10