Datasheet LTC2353-16 (Analog Devices)

LTC2353-16 Buffered Dual, 16-Bit, 550ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
FEATURES DESCRIPTION
n
Simultaneous Sampling of 2 Buffered Channels
The LTC®2353-16 is a 16-bit, low noise 2-channel simulta- n
550ksps per Channel Throughput
neous sampling successive approximation register (SAR) n
500pA/12nA Max Input Leakage at 85°C/125°C
ADC with buffered differential, wide common mode range n
±1LSB INL (Maximum, ±10.24V Range)
picoamp inputs. Operating from a 5V low voltage sup- n
Guaranteed 16-Bit, No Missing Codes
ply, flexible high voltage supplies, and using the internal n
Differential, Wide Common Mode Range Inputs
reference and buffer, both channels of this SoftSpanTM n
Per-Channel SoftSpan Input Ranges:
ADC can be independently configured on a conversion-
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V
by-conversion basis to accept ±10.24V, 0V to 10.24V,
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V
±5.12V, or 0V to 5.12V signals. One channel may also n
94.2dB Single-Conversion SNR (Typical)
be disabled to increase throughput on the other channel. n
−110dB THD (Typical) at fIN = 2kHz
The integrated picoamp-input analog buffers, wide input n
124dB CMRR (Typical) at fIN = 200Hz
common mode range and 124dB CMRR of the LTC2353-16 n
Rail-to-Rail Input Overdrive Tolerance
al ow the ADC to directly digitize a variety of signals us- n Integrated Reference and Buffer (4.096V) ing minimal board space and power. This input signal n SPI CMOS (1.8V to 5V) and LVDS Serial I/O flexibility, combined with ±1LSB INL, no missing codes n Internal Conversion Clock, No Cycle Latency at 16 bits, and 94.2dB SNR, makes the LTC2353-16 an n 162mW Power Dissipation (Typical) ideal choice for many high voltage applications requiring n 48-Lead (7mm x 7mm) LQFP Package wide dynamic range. The LTC2353-16 supports pin-selectable SPI CMOS (1.8V
APPLICATIONS
to 5V) and LVDS serial interfaces. Either one or two lanes n Programmable Logic Controllers of data output may be employed in CMOS mode, allowing n Industrial Process Control the user to optimize bus width and throughput. n All registered trademarks and trademarks are the property of their respective owners. Protected Power Line Monitoring by U.S. Patents, including 7705765, 7961132, 8319673, 9197235. n Test and Measurement
TYPICAL APPLICATION
15V 5V 1.8V TO 5V
Integral Nonlinearity vs
0.1µF 0.1µF 2.2µF 0.1µF
Output Code and Channel
CMOS OR LVDS I/O INTERFACE 1.00 ±10.24V RANGE FULLY VCC VDD VDDLBYP OVDD LVDS/CMOS TRUE BIPOLAR DRIVE (IN– = 0V) 0.75 ARBITRARY DIFFERENTIAL PD BOTH CHANNELS +10V +5V BUFFERS 0.50 LTC2353-16 0V 0V IN0+ S/H 0.25 IN0– –10V –5V SDO0 0 16-BIT MUX SDO1 TRUE BIPOLAR UNIPOLAR SAR ADC SCKO –0.25 +10V +10V INL ERROR (LSB) SCKI IN1+ SDI –0.50 S/H 0V 0V IN1– CS BUSY –0.75 –10V –10V SAMPLE CNV CLOCK VEE REFBUF REFIN GND –1.00 DIFFERENTIAL INPUTS IN+/IN– WITH –32768 –16384 0 16384 32768 235316 TA01a WIDE INPUT COMMON MODE RANGE 47µF 0.1µF OUTPUT CODE TWO BUFFERED 0.1µF 235316 TA01b SIMULTANEOUS SAMPLING CHANNELS –15V 235316f For more information www.linear.com/LTC2353-16 1 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS REFERENCE BUFFER CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS CONFIGURATION TABLES FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION BOARD LAYOUT PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS