Datasheet AD4111 (Analog Devices) - 7

Data Sheet AD4111 Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS Input Voltage4 High, VINH 2 V ≤ IOVDD < 2.3 V 0.65 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 × IOVDD V Low, VINL 2 V ≤ IOVDD < 2.3 V 0.35 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 V Hysteresis4 IOVDD ≥ 2.7 V 0.08 0.25 V IOVDD < 2.7 V 0.04 0.2 V Leakage Current −10 +10 μA LOGIC OUTPUT (DOUT/RDY) Output Voltage High, VOH IOVDD ≥ 4.5 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA 0.8 × IOVDD V IOVDD < 2.7 V, ISOURCE = 200 μA 0.8 × IOVDD V Low, VOL IOVDD ≥ 4.5 V, ISINK = 2 mA 0.4 V 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA 0.4 V IOVDD < 2.7 V, ISINK = 400 μA 0.4 V Leakage Current Floating state −10 +10 μA Output Capacitance Floating state 10 pF POWER REQUIREMENTS Power Supply Voltage AVDD to AVSS 3.0 5.5 V AVSS to DGND −2.75 0 V IOVDD to DGND 2 5.5 V IOVDD to AVSS For AVSS < DGND 6.35 V POWER SUPPLY CURRENTS8 All outputs unloaded, digital inputs connected to IOVDD or DGND Full Operating Mode AVDD Current Including internal reference 3.3 3.7 mA IOVDD Current Internal clock 0.6 0.8 mA Standby Mode All VIN = 0 V 120 μA Power-Down Mode All VIN = 0 V 90 μA POWER DISSIPATION Full Operating Mode 19.5 mW Standby Mode 600 μW Power-Down Mode 450 μW 1 The full specification is guaranteed for a differential input signal of ±10 V. The device is functional up to a differential input signal of ±VREF × 10. However, the specified absolute (pin) voltage must not be exceeded for the proper function. 2 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. 3 The gain calibration register is overwritten by performing an internal full-scale calibration. Alternatively, a system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate for the channel that is calibrated. 4 Specification is not production tested but is supported by characterization data at the initial product release. 5 This maximum specification is only possible if IINx− is biased so that the current through the resistor is less than 24 mA. It is not possible with IINx− connected to 0 V. 6 This specification shows the impedance seen between current input pins. The current is measured across a 50 Ω sense resistor. 7 This specification includes moisture sensitivity level (MSL) preconditioning effects. 8 This specification is with no load on the REFOUT pin and the digital output pins. Rev. 0 | Page 7 of 59 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION THEORY OF OPERATION POWER SUPPLIES Single-Supply Operation (AVSS = DGND) DIGITAL COMMUNICATION AD4111 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register CIRCUIT DESCRIPTION MULTIPLEXER CURRENT INPUTS VOLTAGE INPUTS Fully Differential Inputs Single-Ended Inputs Adjusting Voltage Input Gain Open Wire Detection Example 1—Open Wire Detection (Single-Ended Input) Example 2—Open Wire Detection (Differential Input) Open Wire Detection Compensation Pins DATA OUTPUT CODING AD4111 REFERENCE Internal Reference External Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE OUPUTS DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR ERRORB Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR APPLICATIONS INFORMATION GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE