Datasheet LTM4662 (Analog Devices) - 8

link to page 3 link to page 3 link to page 12 link to page 12 link to page 27 link to page 12 link to page 10 link to page 12 link to page 12 link to page 12 LTM4662
PIN FUNCTIONS (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY
An external clock applied to MODE_PLLIN should be
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
within ±30% of this programmed frequency to ensure
LAYOUT CAREFULLY.
frequency lock. See the Applications Information section.
VOUT1 (H1, J1-J2, K1-K2, L1-L2):
Power Output Pins. Apply output load between these pins and GND pins.
SGND (D3, H3):
Signal Ground Pin. Return ground path Recommend placing output decoupling capacitance for all analog and low power circuitry. Tie a single con- directly between these pins and GND pins. There is a nection to the output capacitor GND in the application. 49.9Ω resistor connected between V See layout guidelines in Figure 19. OUT1 and VOUTS1 to protect the output from an open VOUTS1. Review Table 5.
VFB1 (G4):
This pin is the + input to a unity gain differen- See Note 8 in the Electrical Characteristics section for tial amplifier. This pin is connected to VOUTS1 with a 60.4k output current guideline. precision resistor internal. Different output voltages can be
GND (A3, A6-A7, B3, B6-B7, C3-C7, D6-D7, E6, E8, F5,
programmed with an additional resistor between VFB1 and –
F7, G6, G8, H6-H7, J4-J7, K3, K6-K7, L3, L6-L7 ):
Power VOUTS1 pins. The differential amplifier is feeding back the Ground Pins for Both Input and Output Returns. divided down output voltage from a remote sense divider network to compare to the internal 0.6V reference. In 2-phase
VOUT2 (A1-A2, B1-B2, C1-C2, D1):
Power Output Pins. single output operation, tie the VFB1 pin to INTVCC. See Apply output load between these pins and GND pins. Figure 1 and Applications Information section for details. Recommend placing output decoupling capacitance
V
directly between these pins and GND pins. There is a
FB2 (E4):
This pin is the + input to a non-inverting gain of two amplifier utilizing three resistors in the feedback 49.9Ω resistor connected between VOUT2 and VOUTS2 to network to develop a remote sense divider network. This protect the output from an open VOUTS2. Review Table 5. pin is connected to V See Note 8 in the Electrical Characteristics section for OUTS2 with an internal 60.4k preci- sion resistor. The V output current guideline. OUT2 voltage is divided down to 0.3V then gained back up to 0.6V to compare with the internal
VOUTS1, VOUTS2 (G2, E2):
These pins are connected to 0.6V reference. This technique provides for equivalent the top of the internal top feedback resistor for each out- remote sensing on VOUT2. See Figure 1 and Applications put. Each pin can be directly connected to its specific Information section for details. output, or connected to the remote sense point of VOUT.
TRACK/SS1,TRACK/SS2 (H4, F2):
Output Voltage Tracking It is important to connect these pins to their designated Pin and Soft-Start Inputs. Each channel has a 1.0μA pull-up outputs for proper regulation. current source. Each pin can be programmed with a soft- In paralleling modules, the VOUTS1 pin is left floating, and start ramp rate up to the 0.6V internal reference level, then the VFB1 pin is connected to INTVCC. This will disable chan- beyond this point the internal 0.6V reference will control nel 1’s error amplifier and internally connect COMP1A to the feedback loop. When one channel is configured to be COMP2A. The PGOOD1 and TRACK/SS1 will be disabled master of the two channels, then a capacitor from this pin in this mode. Channel 2’s error amplifier will regulate the to ground will set the soft-start ramp rate. The remaining two channel single output. See VFB pin description and channel can be set up as the slave, and have the master’s Applications Information section. output applied through a voltage divider to the slave out-
FREQ (F1):
Frequency Set Pin. A resistor from this pin to put’s track pin. This voltage divider is equal to the slave SGND sets the operating frequency. The Equation: output’s feedback divider for coincidental tracking. See the Applications Information section. (Recommended to use 41550 – 2.2 = R test points to monitor signal pin connections.) FREQ(kΩ) f(kHz)
DRVCC (G7):
Internal 5.3V regulator output used to source the power MOSFET drivers, and supply power to the INTVCC input. A 4.7µF ceramic capacitor is needed on this pin to GND. Rev. A 8 For more information www.analog.com Document Outline Operation Applications Information Package Description Package Photo Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Package Description Revision History Package Photo Design Resources Related Parts