Datasheet EMC1812, EMC1813, EMC1814, EMC1815, EMC1833 (Microchip) - 9

Multi-Channel Low-Voltage Remote Di... Electrical Characteristics ...continued Characteristic Sym. Min. Typ. Max. Units Conditions
Data Hold Time tHD:DAT 0 — — µs When transmitting to the master Data Hold Time tHD:DAT 0 — — µs When receiving from the master Data Setup Time tSU:DAT 100 — — ns Clock Low-Period tLOW 1.3 — — µs Clock High-Period tHIGH 0.6 — — µs Clock/Data Fall-Time tFALL — — 300 ns Min = 20 + 0.1 CLOAD ns Clock/Data Rise-Time tRISE — — 300 ns Min = 20 + 0.1 CLOAD ns Capacitive Load CLOAD — — 400 pF Per bus line Time-out tTIMEOUT 25 — 35 ms Disabled by default
Figure 1-1. SMBus Timing Diagram
T LOW T HIGH T HD:STA T SU:STO T FALL SCL T RISE T SU:DAT T SU:STA T T HD:STA HD:DAT SDA TBUF P S S - Start Condition S P - Stop Condition P © 2018 Microchip Technology Inc.
Datasheet
DS20005751A-page 9 Document Outline Features Typical Applications Description Package Type Functional Block Diagram Table of Contents 1. Electrical Characteristics 1.1. Absolute Maximum Ratings 2. Typical Operating Curves 3. Pin Descriptions 3.1. Power Supply (VDD) 3.2. Diode 1 Pair (DN1/DP1) 3.3. THERM LIMIT ALERT (THERM/ADDR) 3.4. Ground (GND) 3.5. Maskable ALERT (ALERT/THERM2) 3.6. SMBus/I2C Data (SDA) 3.7. DP/DP1 3.8. DN/DN1 3.9. DP2 3.10. DN2 3.11. Anti-Parallel Diode Pair (DP2/DN3 and DN2/DP3) 3.12. Anti-Parallel Diode Pair (DP1/DN2 and DN1/DP2) 3.13. Anti-Parallel Diode Pair (DP3/DN4 and DN3/DP4) 3.14. SMBus Clock (SCL) 3.15. Exposed Thermal Pad (EP) 4. Detailed Description 5. System Block Diagram 5.1. Temperature Measurement 5.2. Temperature Measurement Results and Data 5.3. Limit Registers 5.4. Limit Register Interaction 5.4.1. High Limit Register 5.4.2. Low Limit Register 5.4.3. THERM Limit Register 5.5. ALERT/THERM2 Output 5.5.1. ALERT/THERM2 Pin Interrupt Mode 5.5.2. ALERT/THERM2 Pin in Therm Mode 5.6. THERM Output 5.7. THERM Pin Address Decoding 5.8. External Diode Connections 5.9. Power States 5.10. Conversion Rates 5.11. Dynamic Averaging 5.12. Digital Filter 5.13. Beta Compensation 5.14. Resistance Error Correction (REC) 5.15. Programmable External Diode Ideality Factor 5.16. Diode Faults 5.17. Consecutive Alerts 5.18. “Hottest Of” Comparison 5.19. Rate of Change 6. System Management Bus Protocol 6.1. SMBus Start Bit 6.2. SMBus Address and RD/WR Bit 6.3. SMBus ACK and NACK Bits 6.3.1. SMBus Data Bytes 6.4. SMBus Stop Bit 6.5. SMBus Time-Out 6.6. SMBus and I2C Compliance 6.7. SMBus Protocols 6.7.1. SMBus Write Byte 6.7.2. Block Write 6.7.3. SMBus Read Byte 6.7.4. Block Read 6.7.5. SMBus Send Byte 6.7.6. SMBus Receive Byte 6.8. THERM Pin Considerations 6.9. Register Summary 6.10. Data Read Interlock 6.10.1. Internal Diode High Byte Data Register (Addresses 00h, 60h) 6.10.2. Internal Diode Low Byte Data Register (Addresses 29h, 61h) 6.10.3. External Diode High Byte Data Register (Addresses 01h, 23h, 2Ah, 32h, 62h, 64h, 66h and 68h) 6.10.4. External Diode Low Byte Data Register (Addresses 10h, 24h, 2Bh, 33h, 63h, 65h, 67h and 69h) 6.10.5. Diode Status Register (Address 02h) 6.10.6. Configuration Register (Addresses 03h and 09h) 6.10.7. Temperature Conversion Rate Register (Addresses 04h and 0Ah) 6.10.8. Internal Diode High Limit Register (Addresses 05h and 0Bh) 6.10.9. Internal Diode Low Limit Register (Addresses 06H and 0CH) 6.10.10. Ext High Limit High Byte Register (Addresses 07h, 0Dh, 15h, 2Ch and 34h) 6.10.11. Ext High Limit Low Byte Register (Addresses 13h, 17h, 2Eh and 36h) 6.10.12. Ext(n) Low Limit High Byte Register (Addresses 08h, 0Eh, 16h, 2Dh and 35h) 6.10.13. Ext(n) Low Limit Low Byte Register (Addresses 14h, 18h, 2fh and 37h) 6.10.14. Scratchpad Register (Addresses 11H and 12H) 6.10.15. One-Shot Register (Address 0FH) 6.10.16. Ext(n) Therm Limit Register (Addresses 19h, 1ah, 30h and 38h) 6.10.17. Internal Diode Therm Limit Register (Address 20h) 6.10.18. Therm Limit Hysteresis Register (Address 21h) 6.10.19. External Diode Fault Status Register (Address 1bh) 6.10.20. Diode Fault Mask Register (Address 1Fh) 6.10.21. Consecutive Alert Register (Address 22h) 6.10.22. Ext(n) Beta Compensation Configuration Register (Address 25h and 26h) 6.10.23. Ext (n) Programmable Ideality Factor Register (Address 27h, 28h, 31h and 39h) 6.10.24. High Limit Status Register (Address 3Ah) 6.10.25. Low Limit Status Register (Address 3Bh) 6.10.26. Therm High Limit Status Register (Address 3Ch) 6.10.27. Rate Of Change Gain Register (Address 3Dh) 6.10.28. Rate Of Change Configuration Register (Address 3Eh) 6.10.29. Rate Of Change Status Register (Address 3Fh) 6.10.30. Rate Of Change Results High Byte Register (n) (Addresses 40h and 44h) 6.10.31. Rate Of Change Results Low Byte Register (Address 45h) 6.10.32. Rate Of Change Alert Limit High Byte Register (n) (Address 41h and 46h) 6.10.33. Rate Of Change Alert Limit Low Byte Register (n) (Address 42h and 47h) 6.10.34. Rate Of Change Samples Register (Address 43h and 48h) 6.10.35. Sample Period Max Temperature High Byte Data Register (Address 49h and 4Bh) 6.10.36. Sample Period Max Temperature Low Byte Data Register (Address 4Ah and 4Ch) 6.10.37. Global Max Temperature High Byte Register (Address 4Dh and 4Fh) 6.10.38. Sample Period Max Temperature Low Byte Data Register (Address 4Eh and 50h) 6.10.39. Filter Selection Register (Address 51h) 6.10.40. Hottest Diode Temperature High Byte Register (Address 6Ah) 6.10.41. Hottest Diode Temperature Low Byte Register (Address 6Bh) 6.10.42. Hottest Diode Status Register (Address 6Ch) 6.10.43. Hottest Diode Configuration Register (Address 6Dh) 6.10.44. Product ID Register (Address FDh) 6.10.45. Manufacturer ID Register (Address FEh) 6.10.46. Revision - Revision Register (Address FFh) 7. Packaging Information 7.1. Package Marking Information 8. Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service