Datasheet AK4376A (Asahi Kasei Microdevices) - 9
| Hersteller | Asahi Kasei Microdevices |
| Beschreibung | Low-Power Advanced 32-bit DAC with HP |
| Seiten / Seite | 68 / 9 — [AK4376A] 6. Absolute Maximum Ratings. (VSS1 = VSS2 = VSS3 = VSS4 = 0 V; … |
| Revision | 00 |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
[AK4376A] 6. Absolute Maximum Ratings. (VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 7, Note 8). Parameter. Symbol. Min. Max. Unit. Power
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[AK4376A] 6. Absolute Maximum Ratings
(VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 7, Note 8)
Parameter
Symbol
Min.
Max.
Unit
Power
Analog
AVDD
4.3
V
0.3
4.3
Supplies:
HP-Amp/Charge Pump
CVDD
V
0.3
4.3
(Note 6)
LDO2 for Digital Core
LVDD
V
0.3
4.3
Digital I/F
TVDD
V
0.3
Input Current, Any Pin Except Supplies
IIN
mA
10
Analog Input Voltage (Note 9)
VINA
AVDD+0.3 or 4.3
V
0.3
Digital Input Voltage (Note 10)
VIND
TVDD+0.3 or 4.3
V
0.3
Ambient Temperature (powered applied)
Ta
85
40
C
Storage Temperature
Tstg
150
65
C
Note 6. Charge pump 1 & 2 are not in operation. In the case that charge pump 1 & 2 are in operation, the
maximum values of AVDD and CVDD become 2.15 V.
Note 7. All voltages with respect to ground.
Note 8. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog plane.
Note 9. XTI pin
The maximum value of input voltage is lower value between (AVDD+0.3)V and 4.3V.
Note 10. MCKI, BCLK, LRCK, SDATA, SCL, SDA, PDN, TESTI1, TESTI2 pins
The maximum value of input voltage is lower value between (TVDD+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
Operation is not guranteed at these extremes. 7. Recommended Operating Conditions
(VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 11)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power
Analog
AVDD
1.7
1.8
1.9
V
supplies
HP-Amp / Charge Pump
CVDD
1.7
1.8
1.9
V
(Note 12) LDO2 for Digital Core
LVDD
1.7
1.8
1.9
V
Digital I/F
TVDD
1.65
1.8
3.6
V
Note 11. All voltages with respect to ground.
Note 12. Each power up/down sequence is shown below. 1. PDN pin = “L”
2. TVDD, AVDD, LVDD, CVDD
(AVDD must be powered up before or at the same time of CVDD. The power-up sequence of
TVDD and LVDD is not critical.)
3. The PDN pin is allowed to be “H” after all power supplies are applied and settled. 1. PDN pin = “L”
2. TVDD, AVDD, LVDD, CVDD
(CVDD must be powered down before or at the same time of AVDD. The power-down
sequence of TVDD and LVDD is not critical.) 016014206-E-00 2016/11
-9-
(VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 7, Note 8)
Parameter
Symbol
Min.
Max.
Unit
Power
Analog
AVDD
4.3
V
0.3
4.3
Supplies:
HP-Amp/Charge Pump
CVDD
V
0.3
4.3
(Note 6)
LDO2 for Digital Core
LVDD
V
0.3
4.3
Digital I/F
TVDD
V
0.3
Input Current, Any Pin Except Supplies
IIN
mA
10
Analog Input Voltage (Note 9)
VINA
AVDD+0.3 or 4.3
V
0.3
Digital Input Voltage (Note 10)
VIND
TVDD+0.3 or 4.3
V
0.3
Ambient Temperature (powered applied)
Ta
85
40
C
Storage Temperature
Tstg
150
65
C
Note 6. Charge pump 1 & 2 are not in operation. In the case that charge pump 1 & 2 are in operation, the
maximum values of AVDD and CVDD become 2.15 V.
Note 7. All voltages with respect to ground.
Note 8. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog plane.
Note 9. XTI pin
The maximum value of input voltage is lower value between (AVDD+0.3)V and 4.3V.
Note 10. MCKI, BCLK, LRCK, SDATA, SCL, SDA, PDN, TESTI1, TESTI2 pins
The maximum value of input voltage is lower value between (TVDD+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
Operation is not guranteed at these extremes. 7. Recommended Operating Conditions
(VSS1 = VSS2 = VSS3 = VSS4 = 0 V; Note 11)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power
Analog
AVDD
1.7
1.8
1.9
V
supplies
HP-Amp / Charge Pump
CVDD
1.7
1.8
1.9
V
(Note 12) LDO2 for Digital Core
LVDD
1.7
1.8
1.9
V
Digital I/F
TVDD
1.65
1.8
3.6
V
Note 11. All voltages with respect to ground.
Note 12. Each power up/down sequence is shown below. 1. PDN pin = “L”
2. TVDD, AVDD, LVDD, CVDD
(AVDD must be powered up before or at the same time of CVDD. The power-up sequence of
TVDD and LVDD is not critical.)
3. The PDN pin is allowed to be “H” after all power supplies are applied and settled. 1. PDN pin = “L”
2. TVDD, AVDD, LVDD, CVDD
(CVDD must be powered down before or at the same time of AVDD. The power-down
sequence of TVDD and LVDD is not critical.) 016014206-E-00 2016/11
-9-