Datasheet ACS71020 (Allegro) - 5
| Hersteller | Allegro |
| Beschreibung | Single Phase, Isolated, Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection |
| Seiten / Seite | 37 / 5 — Single Phase, Isolated, Power Monitoring IC. ACS71020 with Voltage Zero … |
| Dateiformat / Größe | PDF / 1.0 Mb |
| Dokumentensprache | Englisch |
Single Phase, Isolated, Power Monitoring IC. ACS71020 with Voltage Zero Crossing and Overcurrent Detection
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Single Phase, Isolated, Power Monitoring IC ACS71020 with Voltage Zero Crossing and Overcurrent Detection PINOUT DIAGRAM AND TERMINAL LIST Terminal List Table
IP+ 1 16 VINP
Description Number Name
IP+ 2 15 VINN
I2C SPI
IP+ 3 14 GND 1, 2, 3, 4 IP+ Terminals for current being sensed; fused internally IP+ 4 13 VCC 5, 6, 7, 8 IP- Terminals for current being sensed; fused internally IP- 5 12 SDA / MISO 9 DIO_1 / CS Digital I/O 1 Chip Select (CS) IP- 6 11 SCL / SCLK IP- 10 DIO_0 / MOSI Digital I/O 0 MOSI 7 10 DIO_0 / MOSI IP- 8 9 DIO_1 / CS 11 SCL / SCLK SCL SCLK 12 SDA / MISO SDA MISO
Pinout Diagram
13 VCC Device power supply terminal 14 GND Device Power and Signal ground terminal 15 VINN Negative Input Voltage 16 VINP Positive Input Voltage
DIGITAL I/O
The Digital I/O can be programmed to represent the following functions (Digital Output pins are low true): DIO_0: DIO_1: 0. VZC: Voltage zero crossing 0. OCF: Overcurrent fault 1. OVRMS: The VRMS overvoltage flag 1. UVRMS: The VRMS undervoltage flag 2. UVRMS: The VRMS undervoltage flag 2. OVRMS: The VRMS overvoltage flag 3. The OR of OVRMS and UVRMS (if either flag is triggered, 3. The OR of OVRMS, UVRMS, and OCF_LAT [Latched the DIO_0 pin will be asserted) Overcurrent fault] (if any of the three flags are triggered, the DIO_1 pin will be asserted)
VZC DIO_0 OVRMS DIO_0 / MOSI MOSI UVRMS DIO_0_Sel[0..1] Comm_Sel OCF DIO_1 UVRMS DIO_1 / CS OVRMS CS OCF_LAT DIO_1_Sel[0..1] Comm_Sel
Allegro MicroSystems, LLC 5 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing
IP+ 1 16 VINP
Description Number Name
IP+ 2 15 VINN
I2C SPI
IP+ 3 14 GND 1, 2, 3, 4 IP+ Terminals for current being sensed; fused internally IP+ 4 13 VCC 5, 6, 7, 8 IP- Terminals for current being sensed; fused internally IP- 5 12 SDA / MISO 9 DIO_1 / CS Digital I/O 1 Chip Select (CS) IP- 6 11 SCL / SCLK IP- 10 DIO_0 / MOSI Digital I/O 0 MOSI 7 10 DIO_0 / MOSI IP- 8 9 DIO_1 / CS 11 SCL / SCLK SCL SCLK 12 SDA / MISO SDA MISO
Pinout Diagram
13 VCC Device power supply terminal 14 GND Device Power and Signal ground terminal 15 VINN Negative Input Voltage 16 VINP Positive Input Voltage
DIGITAL I/O
The Digital I/O can be programmed to represent the following functions (Digital Output pins are low true): DIO_0: DIO_1: 0. VZC: Voltage zero crossing 0. OCF: Overcurrent fault 1. OVRMS: The VRMS overvoltage flag 1. UVRMS: The VRMS undervoltage flag 2. UVRMS: The VRMS undervoltage flag 2. OVRMS: The VRMS overvoltage flag 3. The OR of OVRMS and UVRMS (if either flag is triggered, 3. The OR of OVRMS, UVRMS, and OCF_LAT [Latched the DIO_0 pin will be asserted) Overcurrent fault] (if any of the three flags are triggered, the DIO_1 pin will be asserted)
VZC DIO_0 OVRMS DIO_0 / MOSI MOSI UVRMS DIO_0_Sel[0..1] Comm_Sel OCF DIO_1 UVRMS DIO_1 / CS OVRMS CS OCF_LAT DIO_1_Sel[0..1] Comm_Sel
Allegro MicroSystems, LLC 5 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing