Datasheet ADSP-BF561 (Analog Devices) - 3

link to page 4 ADSP-BF561 GENERAL DESCRIPTION The ADSP-BF561 processor is a high performance member of The powerful 40-bit shifter has extensive capabilities for per­ the Blackfin® family of products targeting a variety of multime­ forming shifting, rotating, normalization, extraction, and dia, industrial, and telecommunications applications. At the depositing of data. The data for the computational units is heart of this device are two independent Analog Devices found in a multiported register file of sixteen 16-bit entries or Blackfin processors. These Blackfin processors combine a dual- eight 32-bit entries. MAC state-of-the-art signal processing engine, the advantage of A powerful program sequencer controls the flow of instruction a clean, orthogonal RISC-like microprocessor instruction set, execution, including instruction alignment and decoding. The and single instruction, multiple data (SIMD) multimedia capa­ sequencer supports conditional jumps and subroutine calls, as bilities in a single instruction set architecture. well as zero overhead looping. A loop buffer stores instructions The ADSP-BF561 processor has 328K bytes of on-chip memory. locally, eliminating instruction memory accesses for tight Each Blackfin core includes: looped code. • 16K bytes of instruction SRAM/cache Two data address generators (DAGs) provide addresses for • 16K bytes of instruction SRAM simultaneous dual operand fetches from memory. The DAGs share a register file containing four sets of 32-bit Index, Modify, • 32K bytes of data SRAM/cache Length, and Base registers. Eight additional 32-bit registers • 32K bytes of data SRAM provide pointers for general indexing of variables and stack locations. • 4K bytes of scratchpad SRAM Blackfin processors support a modified Harvard architecture in Additional on-chip memory peripherals include: combination with a hierarchical memory structure. Level 1 (L1) • 128K bytes of low latency on-chip L2 SRAM memories are those that typically operate at the full processor • Four-channel internal memory DMA controller speed with little or no latency. Level 2 (L2) memories are other memories, on-chip or off-chip, that may take multiple processor • External memory controller with glueless support for cycles to access. At the L1 level, the instruction memory holds SDRAM, mobile SDRAM, SRAM, and flash. instructions only. The two data memories hold data, and a dedi­
PORTABLE LOW POWER ARCHITECTURE
cated scratchpad data memory stores stack and local variable information. At the L2 level, there is a single unified memory Blackfin processors provide world-class power management space, holding both instructions and data. and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature In addition, half of L1 instruction memory and half of L1 data dynamic power management, the ability to vary both the voltage memory may be configured as either Static RAMs (SRAMs) or and frequency of operation to significantly lower overall power caches. The Memory Management Unit (MMU) provides mem­ consumption. Varying the voltage and frequency can result in a ory protection for individual tasks that may be operating on the substantial reduction in power consumption, compared with core and may protect system registers from unintended access. just varying the frequency of operation. This translates into The architecture provides three modes of operation: user mode, longer battery life for portable appliances. supervisor mode, and emulation mode. User mode has restricted access to certain system resources, thus providing a
BLACKFIN PROCESSOR CORE
protected software environment, while supervisor mode has As shown in Figure 2, each Blackfin core contains two multi­ unrestricted access to the system and core resources. plier/accumulators (MACs), two 40-bit ALUs, four video ALUs, The Blackfin instruction set has been optimized so that 16-bit and a single shifter. The computational units process 8-bit, op-codes represent the most frequently used instructions, 16-bit, or 32-bit data from the register file. resulting in excellent compiled code density. Complex DSP Each MAC performs a 16-bit by 16-bit multiply in every cycle, instructions are encoded into 32-bit op-codes, representing fully with accumulation to a 40-bit result, providing eight bits of featured multifunction instructions. Blackfin processors sup­ extended precision. The ALUs perform a standard set of arith­ port a limited multi-issue capability, where a 32-bit instruction metic and logical operations. With two ALUs capable of can be issued in parallel with two 16-bit instructions, allowing operating on 16-bit or 32-bit data, the flexibility of the computa­ the programmer to use many of the core resources in a single tion units covers the signal processing requirements of a varied instruction cycle. set of application needs. The Blackfin assembly language uses an algebraic syntax for Each of the two 32-bit input registers can be regarded as two ease of coding and readability. The architecture has been opti­ 16-bit halves, so each ALU can accomplish very flexible single mized for use in conjunction with the VisualDSP C/C++ 16-bit arithmetic operations. By viewing the registers as pairs of compiler, resulting in fast and efficient software 16-bit operands, dual 16-bit or single 32-bit operations can be implementations. accomplished in a single cycle. By further taking advantage of the second ALU, quad 16-bit operations can be accomplished simply, accelerating the per cycle throughput. Rev. E | Page 3 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide