Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 8

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ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 3. System Interrupt Controller (SIC) (Continued)
• SIC interrupt wake-up enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral
Default Peripheral
can be configured to wake up the processor, should the
Peripheral Interrupt Event Mapping Interrupt ID
core be idled when the event is generated. (For more infor- DMA Channels 12 and 13 IVG13 29 mation, see Dynamic Power Management on Page 13.) (Memory DMA Stream 0) Because multiple interrupt sources can map to a single general- DMA Channels 14 and 15 IVG13 30 purpose interrupt, multiple pulse assertions can occur simulta- (Memory DMA Stream 1) neously, before or during interrupt processing for an interrupt Software Watchdog Timer IVG13 31 event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt Port F Interrupt B IVG13 31 acknowledgement.
Event Control
The appropriate ILAT register bit is set when an interrupt rising The Blackfin processor provides a very flexible mechanism to edge is detected (detection requires two core clock cycles). The control the processing of events. In the CEC, three registers are bit is cleared when the respective IPEND register bit is set. The used to coordinate and control events. Each register is IPEND bit indicates that the event has entered into the proces- 32 bits wide: sor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The • CEC interrupt latch register (ILAT) – Indicates when minimum latency from the rising edge transition of the general- events have been latched. The appropriate bit is set when purpose interrupt to the IPEND output asserted is three core the processor has latched the event and cleared when the clock cycles; however, the latency can be much higher, depend- event has been accepted into the system. This register is ing on the activity within and the state of the processor. updated automatically by the controller, but it can be writ- ten only when its corresponding IMASK bit is cleared.
DMA CONTROLLERS
• CEC interrupt mask register (IMASK) – Controls the The Blackfin processors have multiple, independent DMA masking and unmasking of individual events. When a bit is channels that support automated data transfers with minimal set in the IMASK register, that event is unmasked and is overhead for the processor core. DMA transfers can occur processed by the CEC when asserted. A cleared bit in the between the processor’s internal memories and any of its DMA- IMASK register masks the event, preventing the processor capable peripherals. Additionally, DMA transfers can be accom- from servicing the event even though the event may be plished between any of the DMA-capable peripherals and latched in the ILAT register. This register can be read or external devices connected to the external memory interfaces, written while in supervisor mode. (Note that general-pur- including the SDRAM controller and the asynchronous mem- pose interrupts can be globally enabled and disabled with ory controller. DMA-capable peripherals include the Ethernet the STI and CLI instructions, respectively.) MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port, • CEC interrupt pending register (IPEND) – The IPEND UARTs, and PPI. Each individual DMA-capable peripheral has register keeps track of all nested events. A set bit in the at least one dedicated DMA channel. IPEND register indicates the event is currently active or The DMA controller supports both one-dimensional (1-D) and nested at some level. This register is updated automatically two-dimensional (2-D) DMA transfers. DMA transfer initial- by the controller but can be read while in supervisor mode. ization can be implemented from registers or from sets of The SIC allows further control of event processing by providing parameters called descriptor blocks. three 32-bit interrupt control and status registers. Each register The 2-D DMA capability supports arbitrary row and column contains a bit corresponding to each of the peripheral interrupt sizes up to 64K elements by 64K elements, and arbitrary row events shown in Table 3 on Page 7. and column step sizes up to ±32K elements. Furthermore, the • SIC interrupt mask register (SIC_IMASK) – Controls the column step size can be less than the row step size, allowing masking and unmasking of each peripheral interrupt event. implementation of interleaved data streams. This feature is When a bit is set in the register, that peripheral event is especially useful in video applications where data can be de- unmasked and is processed by the system when asserted. A interleaved on the fly. cleared bit in the register masks the peripheral event, pre- Examples of DMA types supported by the DMA controller venting the processor from servicing the event. include • SIC interrupt status register (SIC_ISR) – As multiple • A single, linear buffer that stops upon completion peripherals can be mapped to a single event, this register • A circular, auto-refreshing buffer that interrupts on each allows the software to determine which peripheral event full or fractionally full buffer source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- • 1-D or 2-D DMA using a linked list of descriptors cates the peripheral is not asserting the event. • 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page. Rev. J | Page 8 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide