Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 9

link to page 9
ADSP-BF538/ ADSP-BF538F
faces, including the SDRAM controller and the asynchronous The stopwatch function counts down from a programmed memory controller. DMA capable peripherals include the value, with one second resolution. When the stopwatch is SPORTs, SPI ports, UARTs, and PPI. Each individual DMA enabled and the counter underflows, an interrupt is generated. capable peripheral has at least one dedicated DMA channel. Like the other peripherals, the RTC can wake up the processors The DMA controllers support both 1-dimensional (1-D) and from sleep mode upon generation of any RTC wake-up event. 2-dimensional (2-D) DMA transfers. DMA transfer initializa- Additionally, an RTC wake-up event can wake up the processor tion can be implemented from registers or from sets of from deep sleep mode and wake up the on-chip internal voltage parameters called descriptor blocks. regulator from the powered down hibernate state. The 2-D DMA capability supports arbitrary row and column Connect RTC pins RTXI and RTXO with external components sizes up to 64K elements by 64K elements, and arbitrary row as shown in Figure 5. and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing
RTXI RTXO
implementation of interleaved data streams. This feature is especially useful in video applications where data can be
R1
deinterleaved on the fly. Examples of DMA types supported by the processor DMA con-
X1
troller include:
C1 C2
• A single, linear buffer that stops upon completion • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer
SUGGESTED COMPONENTS:
• 1-D or 2-D DMA using a linked list of descriptors
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
• 2-D DMA using an array o f descriptors, specifying only the
C1 = 22pF
base DMA address within a common page
C2 = 22pF R1 = 10M
: In addition to the dedicated peripheral DMA channels, there are
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
four memory DMA channels provided for transfers between the
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
various memories of the ADSP-BF538/ADSP-BF538F proces- sor’s systems. This enables transfers of blocks of data between Figure 5. External Components for RTC any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor interven-
WATCHDOG TIMER
tion. Memory DMA transfers can be controlled by a very The ADSP-BF538/ADSP-BF538F processors include a 32-bit flexible descriptor based methodology or by a standard register timer that can be used to implement a software watchdog func- based autobuffer mechanism. tion. A software watchdog can improve system availability by forcing the processor to a known state through generation of a
REAL-TIME CLOCK
hardware reset, nonmaskable interrupt (NMI), or general-pur- The ADSP-BF538/ADSP-BF538F processors’ real-time clock pose interrupt, if the timer expires before being reset by (RTC) provides a robust set of digital watch features, including software. The programmer initializes the count value of the current time, stopwatch, and alarm. The RTC is clocked by a timer, enables the appropriate interrupt, then enables the timer. 32.768 kHz crystal external to the processor. The RTC periph- Thereafter, the software must reload the counter before it eral has dedicated power supply pins so that it can remain counts to zero from the programmed value. This protects the powered up and clocked even when the rest of the processors system from remaining in an unknown state where software, are in a low power state. The RTC provides several programma- which would normally reset the timer, has stopped running due ble interrupt options, including interrupt per second, minute, to an external noise condition or software error. hour, or day clock ticks, interrupt on programmable stopwatch If configured to generate a hardware reset, the watchdog timer countdown, or interrupt at a programmed alarm time. resets both the core and the processor peripherals. After a reset, The 32.768 kHz input clock frequency is divided down to a 1 Hz software can determine if the watchdog was the source of the signal by a prescaler. The counter function of the timer consists hardware reset by interrogating a status bit in the watchdog of four counters: a 60 second counter, a 60 minute counter, a 24 timer control register. hour counter, and a 32,768 day counter. The timer is clocked by the system clock (SCLK) at a maximum When enabled, the alarm function generates an interrupt when frequency of fSCLK. the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is
TIMERS
for a time of day. The second alarm is for a day and time of that There are four general-purpose programmable timer units in day. the ADSP-BF538/ADSP-BF538F processors. Three timers have an external pin that can be configured either as a pulse-width modulator (PWM) or timer output, as an input to clock the Rev. E | Page 9 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide