Datasheet ADSP-BF542, ADSP-BF544, ADSP-BF547, ADSP-BF548, ADSP-BF549 (Analog Devices) - 3

link to page 3 link to page 3 link to page 3
ADSP-BF542 /ADSP-BF544 /ADSP-BF547/ ADSP-BF548 /ADSP-BF549 GENERAL DESCRIPTION
The ADSP-BF54x Blackfin® processors are members of the Specific peripherals for ADSP-BF54x Blackfin processors are Blackfin family of products, incorporating the Analog Devices/ shown in Table 2. Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine,
Table 2. Specific Peripherals for ADSP-BF54x Processors
the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD)
9 8 7 4 2 4 4 4 4 4
multimedia capabilities into a single instruction-set architecture.
-BF5 -BF5 -BF5 -BF5 -BF5
Specific performance, memory configurations, and features of ADSP-BF54x Blackfin processors are shown in Table 1.
Module ADSP ADSP ADSP ADSP ADSP
E BIU (async) P P P P P
Table 1. ADSP-BF54x Processor Features
NA ND fl ash controller P P P P P ATAPI P P P – P H ost D MA p ort (HOSTDP) P P P P –
-BF549 -BF548 -BF547 -BF544 -BF542
SD/SDIO controller P P P – P EPPI0 P P P P –
Processor Features ADSP ADSP ADSP ADSP ADSP
EPPI1 P P P P P Lockbox® 1code security 1 1 1 1 1 EPPI2 P P P P P 128 -bit A ES/ AR C4 d ata encryption 1 1 1 1 1 SPORT0 P P P – – SD/SDIO controller 1 1 1 – 1 SPORT1 P P P P P Pixel compositor 1 1 1 1 1 SPORT2 P P P P P 18- or 24-bit EPPI0 with LCD 1 1 1 1 – SPORT3 P P P P P 16-bit EPPI1, 8-bit EPPI2 1 1 1 1 1 SPI0 P P P P P Host DMA port 1 1 1 1 – SPI1 P P P P P NAND flash controller 1 1 1 1 1 SPI2 P P P – – ATAPI 1 1 1 – 1 UART0 P P P P P High speed USB OTG 1 1 1 – 1 UART1 P P P P P Keypad interface 1 1 1 – 1 UART2 P P P – – MXVR 1 – – – – UART3 P P P P P CAN ports 2 2 – 2 1 H igh sp eed U SB OTG P P P – P T WI ports 2 2 2 2 1 CAN0 P P – P P SPI ports 3 3 3 2 2 CAN1 P P – P – UA RT ports 4 4 4 3 3 TWI0 P P P P P SPORTs 4 4 4 3 3 TWI1 P P P P – Up/do wn counter 1 1 1 1 1 Tim er 0–7 P P P P P Timers 11 11 11 11 8 Tim er 8–10 P P P P – General-purpose I/O pins 152 152 152 152 152 Up/do wn counter P P P P P Memory L1 Instruction SRAM/cache 16 16 16 16 16 Configura- Keypad interface P P P – P L1 Instruction SRAM 48 48 48 48 48 tions MXVR P – – – – L1 Data SRAM/cache 32 32 32 32 32 (K Bytes) GPIOs P P P P P L1 Data SRAM 32 32 32 32 32 L1 Scratchp ad SRAM 4 4 4 4 4 L1 ROM2 64 64 64 64 64 L2 128 128 128 64 – L3 Boot ROM2 4 4 4 4 4 Maximum core instruction rate (MHz) 533 533 600 533 600 1 Lockbox is a registered trademark of Analog Devices, Inc. 2 This ROM is not customer-configurable. Rev. E | Page 3 of 102 | March 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory One-Time-Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Interface Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports UART Ports (UARTs) Controller Area Network (CAN) TWI Controller Interface Ports General-Purpose I/O (GPIO) Pin Interrupts Pixel Compositor (PIXC) Enhanced Parallel Peripheral Interface (EPPI) USB On-the-Go Dual-Role Device Controller ATA/ATAPI-6 Interface Keypad Interface Secure Digital (SD)/SDIO Controller Code Security Media Transceiver MAC Layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Domains Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) MXVR Board Layout Guidelines Additional information Related Signal Chains Lockbox Secure Technology Disclaimer Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing DDR SDRAM/Mobile DDR SDRAM Timing DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing External Port Bus Request and Grant Cycle Timing NAND Flash Controller Interface Timing Synchronous Burst AC Timing External DMA Request Timing Enhanced Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing SD/SDIO Controller Timing MXVR Timing HOSTDP A/C Timing-Host Read Cycle HOSTDP A/C Timing-Host Write Cycle ATA/ATAPI-6 Interface Timing USB On-The-Go-Dual-Role Device Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Typical Rise and Fall Times Thermal Characteristics 400-Ball CSP_BGA Package Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide