Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | Blackfin Embedded Processor |
| Seiten / Seite | 88 / 2 — ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527. TABLE … |
| Revision | D |
| Dateiformat / Größe | PDF / 3.0 Mb |
| Dokumentensprache | Englisch |
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527. TABLE OF CONTENTS. REVISION HISTORY. 7/13—Rev. C to Rev. D
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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TABLE OF CONTENTS
Features ... 1 Clock Signals .. 16 Memory .. 1 Booting Modes ... 18 Peripherals ... 1 Instruction Set Description .. 20 General Description ... 3 Development Tools .. 20 Portable Low Power Architecture ... 3 Additional Information .. 21 System Integration .. 3 Related Signal Chains ... 22 Processor Peripherals ... 3 Lockbox Secure Technology Disclaimer .. 22 Blackfin Processor Core .. 4 Signal Descriptions ... 23 Memory Architecture .. 5 Specifications .. 28 DMA Controllers .. 9 Operating Conditions Host DMA Port .. 9 for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors .. 28 Real-Time Clock ... 9 Operating Conditions for ADSP-BF523/ADSP-BF525/ Watchdog Timer .. 10 ADSP-BF527 Processors .. 30 Timers ... 10 Electrical Characteristics ... 32 Up/Down Counter and Thumbwheel Interface .. 10 Absolute Maximum Ratings ... 37 Serial Ports .. 10 Package Information .. 38 Serial Peripheral Interface (SPI) Port ... 11 ESD Sensitivity ... 38 UART Ports .. 11 Timing Specifications ... 39 TWI Controller Interface .. 12 Output Drive Currents ... 73 10/100 Ethernet MAC .. 12 Test Conditions .. 75 Ports .. 12 Environmental Conditions .. 79 Parallel Peripheral Interface (PPI) ... 13 289-Ball CSP_BGA Ball Assignment ... 80 USB On-The-Go Dual-Role Device Controller ... 14 208-Ball CSP_BGA Ball Assignment ... 83 Code Security with Lockbox Secure Technology ... 14 Outline Dimensions .. 86 Dynamic Power Management .. 14 Surface-Mount Design .. 87 ADSP-BF523/ADSP-BF525/ADSP-BF527 Automotive Products .. 87 Voltage Regulation ... 16 Ordering Guide ... 88 ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation ... 16
REVISION HISTORY 7/13—Rev. C to Rev. D
Updated Development Tools .. 20 Corrected footnote 9 and added footnote 11 in Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors .. 30 Rev. D | Page 2 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 TABLE OF CONTENTS
Features ... 1 Clock Signals .. 16 Memory .. 1 Booting Modes ... 18 Peripherals ... 1 Instruction Set Description .. 20 General Description ... 3 Development Tools .. 20 Portable Low Power Architecture ... 3 Additional Information .. 21 System Integration .. 3 Related Signal Chains ... 22 Processor Peripherals ... 3 Lockbox Secure Technology Disclaimer .. 22 Blackfin Processor Core .. 4 Signal Descriptions ... 23 Memory Architecture .. 5 Specifications .. 28 DMA Controllers .. 9 Operating Conditions Host DMA Port .. 9 for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors .. 28 Real-Time Clock ... 9 Operating Conditions for ADSP-BF523/ADSP-BF525/ Watchdog Timer .. 10 ADSP-BF527 Processors .. 30 Timers ... 10 Electrical Characteristics ... 32 Up/Down Counter and Thumbwheel Interface .. 10 Absolute Maximum Ratings ... 37 Serial Ports .. 10 Package Information .. 38 Serial Peripheral Interface (SPI) Port ... 11 ESD Sensitivity ... 38 UART Ports .. 11 Timing Specifications ... 39 TWI Controller Interface .. 12 Output Drive Currents ... 73 10/100 Ethernet MAC .. 12 Test Conditions .. 75 Ports .. 12 Environmental Conditions .. 79 Parallel Peripheral Interface (PPI) ... 13 289-Ball CSP_BGA Ball Assignment ... 80 USB On-The-Go Dual-Role Device Controller ... 14 208-Ball CSP_BGA Ball Assignment ... 83 Code Security with Lockbox Secure Technology ... 14 Outline Dimensions .. 86 Dynamic Power Management .. 14 Surface-Mount Design .. 87 ADSP-BF523/ADSP-BF525/ADSP-BF527 Automotive Products .. 87 Voltage Regulation ... 16 Ordering Guide ... 88 ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation ... 16
REVISION HISTORY 7/13—Rev. C to Rev. D
Updated Development Tools .. 20 Corrected footnote 9 and added footnote 11 in Operating Conditions for ADSP-BF523/ADSP-BF525/ ADSP-BF527 Processors .. 30 Rev. D | Page 2 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide