Datasheet ADSP-BF592 (Analog Devices) - 6

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ADSP-BF592
• Exceptions – Events that occur synchronously to program The processor DMA controller supports both one-dimensional flow (in other words, the exception is taken before the (1-D) and two-dimensional (2-D) DMA transfers. DMA trans- instruction is allowed to complete). Conditions such as fer initialization can be implemented from registers or from sets data alignment violations and undefined instructions cause of parameters called descriptor blocks. exceptions. The 2-D DMA capability supports arbitrary row and column • Interrupts – Events that occur asynchronously to program sizes up to 64K elements by 64K elements, and arbitrary row flow. They are caused by input signals, timers, and other and column step sizes up to ±32K elements. Furthermore, the peripherals, as well as by an explicit software instruction. column step size can be less than the row step size, allowing Each event type has an associated register to hold the return implementation of interleaved data streams. This feature is address and an associated return-from-event instruction. When especially useful in video applications where data can be de- an event is triggered, the state of the processor is saved on the interleaved on the fly. supervisor stack. Examples of DMA types supported by the processor DMA con- The processor event controller consists of two stages: the core troller include: event controller (CEC) and the system interrupt controller • A single, linear buffer that stops upon completion (SIC). The core event controller works with the system interrupt • A circular, auto-refreshing buffer that interrupts on each controller to prioritize and control all system events. Conceptu- full or fractionally full buffer ally, interrupts from the peripherals enter into the SIC and are then routed directly into the general-purpose interrupts of the • 1-D or 2-D DMA using a linked list of descriptors CEC. • 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page
Core Event Controller (CEC)
In addition to the dedicated peripheral DMA channels, there are The CEC supports nine general-purpose interrupts (IVG15–7), two memory DMA channels, which are provided for transfers in addition to the dedicated interrupt and exception events. Of between the various memories of the processor system with these general-purpose interrupts, the two lowest priority minimal processor intervention. Memory DMA transfers can be interrupts (IVG15–14) are recommended to be reserved for controlled by a very flexible descriptor-based methodology or software interrupt handlers, leaving seven prioritized interrupt by a standard register-based autobuffer mechanism. inputs to support the peripherals of the processor. The inputs to the CEC, their names in the event vector table (EVT), and their
PROCESSOR PERIPHERALS
priorities are described in the ADSP-BF59x Blackfin Processor The ADSP-BF592 processor contains a rich set of peripherals Hardware Reference, “System Interrupts” chapter. connected to the core via several high bandwidth buses, provid-
System Interrupt Controller (SIC)
ing flexibility in system configuration, as well as excellent overall system performance (see Figure 1). The processor also The system interrupt controller provides the mapping and rout- contains dedicated communication modules and high speed ing of events from the many peripheral interrupt sources to the serial and parallel ports, an interrupt controller for flexible man- prioritized general-purpose interrupt inputs of the CEC. agement of interrupts from the on-chip peripherals or external Although the processor provides a default mapping, the user sources, and power management control functions to tailor the can alter the mappings and priorities of interrupt events by writ- performance and power characteristics of the processor and sys- ing the appropriate values into the interrupt assignment tem to many application scenarios. registers (SIC_IARx). The inputs into the SIC and the default mappings into the CEC are described in the ADSP-BF59x Black- The SPORTs, SPIs, UART, and PPI peripherals are supported fin Processor Hardware Reference, “System Interrupts” chapter. by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the proces- The SIC allows further control of event processing by providing sor’s various memory spaces, including boot ROM. Multiple three pairs of 32-bit interrupt control and status registers. Each on-chip buses running at up to 100 MHz provide enough band- register contains a bit, corresponding to each peripheral inter- width to keep the processor core running along with activity on rupt event. For more information, see the ADSP-BF59x Blackfin all of the on-chip and external peripherals. Processor Hardware Reference, “System Interrupts” chapter. The ADSP-BF592 processor includes an interface to an off-chip
DMA CONTROLLERS
voltage regulator in support of the processor’s dynamic power The processor has multiple, independent DMA channels that management capability. support automated data transfers with minimal overhead for
Watchdog Timer
the processor core. DMA transfers can occur between the pro- cessor’s internal memories and any of its DMA-capable The processor includes a 32-bit timer that can be used to imple- peripherals. DMA-capable peripherals include the SPORTs, SPI ment a software watchdog function. A software watchdog can ports, UART, and PPI. Each individual DMA-capable periph- improve system availability by forcing the processor to a known eral has at least one dedicated DMA channel. state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The programmer Rev. B | Page 6 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide