Datasheet LTC3728 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator |
| Seiten / Seite | 36 / 8 — TYPICAL PERFORMANCE CHARACTERISTICS. Undervoltage Lockout. Shutdown Latch … |
| Dateiformat / Größe | PDF / 1.7 Mb |
| Dokumentensprache | Englisch |
TYPICAL PERFORMANCE CHARACTERISTICS. Undervoltage Lockout. Shutdown Latch Thresholds. vs Temperature
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LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout Shutdown Latch Thresholds vs Temperature vs Temperature
3.50 4.5 4.0 LATCH ARMING 3.45 3.5 3.40 3.0 LATCHOFF THRESHOLD 2.5 3.35 2.0 3.30 1.5 UNDERVOLTAGE LOCKOUT (V) 1.0 3.25 SHUTDOWN LATCH THRESHOLDS (V) 0.5 3.20 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3728 G29 3728 G30
PIN FUNCTIONS G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13):
Combination with 50kΩ. The phase-locked loop will force the rising of soft-start, run control inputs and short-circuit detection top gate signal of controller 1 to be synchronized with timers. A capacitor to ground at each of these pins sets the the rising edge of the PLLIN signal. ramp time to full output current. Forcing either of these pins
FCB (Pin 7/Pin 4):
Forced Continuous Control Input. back below 1.0V causes the IC to shut down the circuitry This input acts on both controllers and is normally used required for that particular controller. Latchoff overcurrent to regulate a secondary winding. Pulling this pin below protection is also invoked via this pin as described in the 0.8V will force continuous synchronous operation. Applications Information section.
I SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12):
The (+)
TH1, ITH2 (Pins 8, 11/Pins 5, 8):
Error Amplifi er Output Input to the Differential Current Comparators. The I and Switching Regulator Compensation Point. Each as- TH pin voltage and controlled offsets between the SENSE– and sociated channels’ current comparator trip point increases SENSE+ pins in conjunction with R with this control voltage. SENSE set the current trip threshold.
SGND (Pin 9/Pin 6):
Small Signal Ground common to
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11):
The (–) both controllers, must be routed separately from high Input to the Differential Current Comparators. current grounds to the common (–) terminals of the COUT capacitors.
VOSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9):
Receives the remotely-sensed feedback voltage for each controller from
3.3VOUT (Pin 10/Pin 7):
Output of a linear regulator ca- an external resistive divider across the output. pable of supplying 10mA DC with peak currents as high as 50mA.
PLLFLTR (Pin 5/Pin 2):
The Phase-Locked Loop’s Lowpass Filter is Tied to This Pin. Alternatively, this pin can be driven
NC (Pins 10, 16, 29, 32 UH Package Only):
No Connect. with an AC or DC voltage source to vary the frequency of
PGND (Pin 20/Pin 19):
Driver Power Ground. Connects to the internal oscillator. the sources of bottom (synchronous) N-channel MOSFETs,
PLLIN (Pin 6/Pin 3):
External Synchronization Input to anodes of the Schottky rectifi ers and the (–) terminal(s) Phase Detector. This pin is internally terminated to SGND of CIN. 3728fg 8
TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout Shutdown Latch Thresholds vs Temperature vs Temperature
3.50 4.5 4.0 LATCH ARMING 3.45 3.5 3.40 3.0 LATCHOFF THRESHOLD 2.5 3.35 2.0 3.30 1.5 UNDERVOLTAGE LOCKOUT (V) 1.0 3.25 SHUTDOWN LATCH THRESHOLDS (V) 0.5 3.20 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3728 G29 3728 G30
PIN FUNCTIONS G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13):
Combination with 50kΩ. The phase-locked loop will force the rising of soft-start, run control inputs and short-circuit detection top gate signal of controller 1 to be synchronized with timers. A capacitor to ground at each of these pins sets the the rising edge of the PLLIN signal. ramp time to full output current. Forcing either of these pins
FCB (Pin 7/Pin 4):
Forced Continuous Control Input. back below 1.0V causes the IC to shut down the circuitry This input acts on both controllers and is normally used required for that particular controller. Latchoff overcurrent to regulate a secondary winding. Pulling this pin below protection is also invoked via this pin as described in the 0.8V will force continuous synchronous operation. Applications Information section.
I SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12):
The (+)
TH1, ITH2 (Pins 8, 11/Pins 5, 8):
Error Amplifi er Output Input to the Differential Current Comparators. The I and Switching Regulator Compensation Point. Each as- TH pin voltage and controlled offsets between the SENSE– and sociated channels’ current comparator trip point increases SENSE+ pins in conjunction with R with this control voltage. SENSE set the current trip threshold.
SGND (Pin 9/Pin 6):
Small Signal Ground common to
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11):
The (–) both controllers, must be routed separately from high Input to the Differential Current Comparators. current grounds to the common (–) terminals of the COUT capacitors.
VOSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9):
Receives the remotely-sensed feedback voltage for each controller from
3.3VOUT (Pin 10/Pin 7):
Output of a linear regulator ca- an external resistive divider across the output. pable of supplying 10mA DC with peak currents as high as 50mA.
PLLFLTR (Pin 5/Pin 2):
The Phase-Locked Loop’s Lowpass Filter is Tied to This Pin. Alternatively, this pin can be driven
NC (Pins 10, 16, 29, 32 UH Package Only):
No Connect. with an AC or DC voltage source to vary the frequency of
PGND (Pin 20/Pin 19):
Driver Power Ground. Connects to the internal oscillator. the sources of bottom (synchronous) N-channel MOSFETs,
PLLIN (Pin 6/Pin 3):
External Synchronization Input to anodes of the Schottky rectifi ers and the (–) terminal(s) Phase Detector. This pin is internally terminated to SGND of CIN. 3728fg 8