Datasheet LTC3736 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Dual 2-Phase, No RSENSE , Synchronous Controller with Output Tracking |
| Seiten / Seite | 28 / 6 — TYPICAL PERFOR A CE CHARACTERISTICS TA = 25. C unless otherwise noted. … |
| Dateiformat / Größe | PDF / 447 Kb |
| Dokumentensprache | Englisch |
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25. C unless otherwise noted. Shutdown Quiescent Current. RUN/SS Start-Up Current
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LTC3736
W U TYPICAL PERFOR A CE CHARACTERISTICS TA = 25
°
C unless otherwise noted. Shutdown Quiescent Current RUN/SS Start-Up Current vs Input Voltage vs Input Voltage
20 0.9 RUN/SS = 0V RUN/SS = 0V 18 A) 0.8 µ 16 A) 0.7 µ 14 0.6 12 0.5 10 0.4 8 6 0.3 SHUTDOWN CURRENT ( 4 0.2 2 RUN/SS PIN PULL-UP CURRENT ( 0.1 0 0 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3736 G17 3736 G18
U U U PI FU CTIO S (UF/GN Package) ITH1/ITH2 (Pins 1, 8/ Pins 4, 11):
Current Threshold and with values equal to those connected to VFB2 from VOUT2 Error Amplifier Compensation Point. Nominal operating should be used to connect to TRACK from VOUT1. range on these pins is from 0.7V to 2V. The voltage on
PGOOD(Pin 9/Pin 12):
Power Good Output Voltage Moni- these pins determines the threshold of the main current tor Open-Drain Logic Output. This pin is pulled to ground comparator. when the voltage on either feedback pin (VFB1, VFB2) is not
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter. within ±13.3% of its nominal set point. When synchronizing to an external clock, this pin serves
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23):
Power as the lowpass filter point for the phase-locked loop. Nor- Ground. These pins serve as the ground connection for the mally a series RC is connected between this pin and ground. gate drivers and the negative input to the reverse current When not synchronizing to an external clock, this pin serves comparators. The Exposed Pad (UF package) must be as the frequency select input. Tying this pin to GND selects soldered to PCB ground. 300kHz operation; tying this pin to VIN selects 750kHz op-
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional eration. Floating this pin selects 550kHz operation. External Soft-Start Input. Forcing this pin below 0.65V shuts
SGND (Pin 4/Pin 7):
Small-Signal Ground. This pin serves down the chip (both channels). Driving this pin to VIN or as the ground connection for most internal circuits. releasing this pin enables the chip, using the chip’s inter-
V
nal soft-start. An external soft-start can be programmed by
IN (Pin 5/Pin 8):
Chip Signal Power Supply. This pin powers the entire chip except for the gate drivers. Externally connecting a capacitor between this pin and ground. filtering this pin with a lowpass RC network (e.g.,
TG1/TG2 (Pins 17, 15/Pins 20, 18):
Top (PMOS) Gate Drive R = 10Ω, C = 1µF) is suggested to minimize noise pickup, Output. These pins drive the gates of the external P-channel especially in high load current applications. MOSFETs. These pins have an output swing from PGND to
TRACK (Pin 6/Pin 9):
Tracking Input for Second Control- SENSE+. ler. Allows the start-up of VOUT2 to “track” that of VOUT1
SYNC/FCB (Pin 18/Pin 21):
This pin performs three according to a ratio established by a resistor divider on functions: 1) auxiliary winding feedback input, 2) external VOUT1 connected to the TRACK pin. For one-to-one track- clock synchronization input for phase-locked loop, and 3) ing of VOUT1 and VOUT2 during start-up, a resistor divider Burst Mode operation or forced continuous mode select. 3736fa 6
W U TYPICAL PERFOR A CE CHARACTERISTICS TA = 25
°
C unless otherwise noted. Shutdown Quiescent Current RUN/SS Start-Up Current vs Input Voltage vs Input Voltage
20 0.9 RUN/SS = 0V RUN/SS = 0V 18 A) 0.8 µ 16 A) 0.7 µ 14 0.6 12 0.5 10 0.4 8 6 0.3 SHUTDOWN CURRENT ( 4 0.2 2 RUN/SS PIN PULL-UP CURRENT ( 0.1 0 0 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3736 G17 3736 G18
U U U PI FU CTIO S (UF/GN Package) ITH1/ITH2 (Pins 1, 8/ Pins 4, 11):
Current Threshold and with values equal to those connected to VFB2 from VOUT2 Error Amplifier Compensation Point. Nominal operating should be used to connect to TRACK from VOUT1. range on these pins is from 0.7V to 2V. The voltage on
PGOOD(Pin 9/Pin 12):
Power Good Output Voltage Moni- these pins determines the threshold of the main current tor Open-Drain Logic Output. This pin is pulled to ground comparator. when the voltage on either feedback pin (VFB1, VFB2) is not
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter. within ±13.3% of its nominal set point. When synchronizing to an external clock, this pin serves
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23):
Power as the lowpass filter point for the phase-locked loop. Nor- Ground. These pins serve as the ground connection for the mally a series RC is connected between this pin and ground. gate drivers and the negative input to the reverse current When not synchronizing to an external clock, this pin serves comparators. The Exposed Pad (UF package) must be as the frequency select input. Tying this pin to GND selects soldered to PCB ground. 300kHz operation; tying this pin to VIN selects 750kHz op-
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional eration. Floating this pin selects 550kHz operation. External Soft-Start Input. Forcing this pin below 0.65V shuts
SGND (Pin 4/Pin 7):
Small-Signal Ground. This pin serves down the chip (both channels). Driving this pin to VIN or as the ground connection for most internal circuits. releasing this pin enables the chip, using the chip’s inter-
V
nal soft-start. An external soft-start can be programmed by
IN (Pin 5/Pin 8):
Chip Signal Power Supply. This pin powers the entire chip except for the gate drivers. Externally connecting a capacitor between this pin and ground. filtering this pin with a lowpass RC network (e.g.,
TG1/TG2 (Pins 17, 15/Pins 20, 18):
Top (PMOS) Gate Drive R = 10Ω, C = 1µF) is suggested to minimize noise pickup, Output. These pins drive the gates of the external P-channel especially in high load current applications. MOSFETs. These pins have an output swing from PGND to
TRACK (Pin 6/Pin 9):
Tracking Input for Second Control- SENSE+. ler. Allows the start-up of VOUT2 to “track” that of VOUT1
SYNC/FCB (Pin 18/Pin 21):
This pin performs three according to a ratio established by a resistor divider on functions: 1) auxiliary winding feedback input, 2) external VOUT1 connected to the TRACK pin. For one-to-one track- clock synchronization input for phase-locked loop, and 3) ing of VOUT1 and VOUT2 during start-up, a resistor divider Burst Mode operation or forced continuous mode select. 3736fa 6