Datasheet LTC3727A-1 (Analog Devices) - 8

LTC3727A-1
PIN FUNCTIONS RUN/SS1, RUN/SS2 (Pins 1, 15):
Combination of
3.3VOUT (Pin 10):
Linear Regulator Output. Capable of Soft-Start, Run Control Inputs. A capacitor to ground at supplying 10mA DC with peak currents as high as each of these pins sets the ramp time to full output current. 50mA. Forcing either of these pins back below 1.0V causes the
PGND (Pin 20):
Driver Power Ground. Connects to the IC to shut down the circuitry required for that particular sources of bottom (synchronous) N-channel MOSFETs, controller. anodes of the Schottky rectifi ers and the (–) terminal(s)
SENSE1+, SENSE2+ (Pins 2, 14):
The (+) Input to the of CIN. Differential Current Comparators. The ITH pin voltage and
INTV
controlled offsets between the SENSE– and SENSE+ pins in
CC (Pin 21):
Output of the Internal 7.5V Linear Low Dropout Regulator and the EXTV conjunction with R CC Switch. The driver and SENSE set the current trip threshold. control circuits are powered from this voltage source. Must
SENSE1–, SENSE2– (Pins 3, 13):
The (–) Input to the be decoupled to power ground with a minimum of 4.7μF Differential Current Comparators. tantalum or other low ESR capacitor.
VOSENSE1, VOSENSE2 (Pins 4, 12):
Receives the
EXTVCC (Pin 22):
External Power Input to an Internal remotely-sensed feedback voltage for each controller from Switch Connected to INTVCC. This switch closes and an external resistive divider across the output. supplies VCC power, bypassing the internal low dropout regulator, whenever EXTV
PLLFLTR (Pin 5):
The phase-locked loop’s lowpass fi lter CC is higher than 7.3V. See EXTV is tied to this pin. Alternatively, this pin can be driven with CC connection in Applications section. Do not exceed 8.5V on this pin. an AC or DC voltage source to vary the frequency of the internal oscillator.
BG1, BG2 (Pins 23, 19):
High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing
PLLIN (Pin 6):
External Synchronization Input to Phase at these pins is from ground to INTV Detector. This pin is internally terminated to SGND with CC. 100kΩ. The phase-locked loop will force the rising top
VIN (Pin 24):
Main Supply Pin. A bypass capacitor should gate signal of controller 1 to be synchronized with the be tied between this pin and the signal ground pin. rising edge of the PLLIN signal.
BOOST1, BOOST2 (Pins 25, 18):
Bootstrapped Supplies
FCB (Pin 7):
Forced Continuous Control Input. This input to the Top Side Floating Drivers. Capacitors are connected acts on both controllers and is normally used to regulate between the boost and switch pins and Schottky diodes are a secondary winding. Pulling this pin below 0.8V will tied between the boost and INTVCC pins. Voltage swing at force continuous synchronous operation. Do not leave the boost pins is from INTVCC to (VIN + INTVCC). this pin fl oating.
SW1, SW2 (Pins 26, 17):
Switch Node Connections to
ITH1, ITH2 (Pins 8, 11):
Error Amplifi er Outputs and Inductors. Voltage swing at these pins is from a Schottky Switching Regulator Compensation Points. Each associ- diode (external) voltage drop below ground to VIN. ated channels’ current comparator trip point increases
TG1, TG2 (Pins 27, 16):
High Current Gate Drives for with this control voltage. Top N-Channel MOSFETs. These are the outputs of
SGND (Pin 9):
Small Signal Ground. Common to fl oating drivers with a voltage swing equal to INTVCC – 0.5V both controllers; must be routed separately from high superimposed on the switch node voltage SW. current grounds to the common (–) terminals of the
PGOOD (Pin 28):
Open-Drain Logic Output. PGOOD is COUT capacitors. pulled to ground when the voltage on either VOSENSE pin is not within ±7.5% of its set point. 3727a1fa 8