Datasheet LTC3736-2 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Dual 2-Phase, No RSENSE , Synchronous Controller with Output Tracking |
| Seiten / Seite | 28 / 6 — TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. … |
| Dateiformat / Größe | PDF / 357 Kb |
| Dokumentensprache | Englisch |
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Undervoltage Lockout Threshold
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LTC3736-2
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Undervoltage Lockout Threshold Shutdown Quiescent Current RUN/SS Start-Up Current vs Temperature vs Input Voltage vs Input Voltage
2.50 20 0.9 RUN/SS = 0V RUN/SS = 0V 18 2.45 0.8 VIN RISING 16 0.7 2.40 14 0.6 2.35 12 0.5 ) VOLTAGE (V) 2.30 10 IN VIN FALLING 0.4 8 2.25 0.3 6 INPUT (V 2.20 SHUTDOWN CURRENT (μA) 4 0.2 2.15 2 RUN/SS PIN PULL-UP CURRENT (μA) 0.1 2.10 0 0 –60 –40 –20 0 20 40 60 80 100 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 TEMPERATURE (°C) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 37362 G16 37362 G17 37362 G18
PIN FUNCTIONS (QFN/SSOP Package) ITH1/ ITH2 (Pins 1, 8/Pins 4, 11):
Current Threshold and values equal to those connected to VFB2 from VOUT2 should Error Amplifi er Compensation Point. Nominal operating be used to connect to TRACK from VOUT1. range on these pins is from 0.7V to 2V. The voltage on
PGOOD (Pin 9/Pin 12):
Power Good Output Voltage Moni- these pins determines the threshold of the main current tor Open-Drain Logic Output. This pin is pulled to ground comparator. when the voltage on either feedback pin (VFB1, VFB2) is
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter. not within ±13.3% of its nominal set point. When synchronizing to an external clock, this pin serves as
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23):
Power the lowpass fi lter point for the phase-locked loop. Normally Ground. These pins serve as the ground connection for a series RC is connected between this pin and ground. the gate drivers and the negative input to the reverse cur- When not synchronizing to an external clock, this pin serves rent comparators. The Exposed Pad must be soldered to as the frequency select input. Tying this pin to GND selects PCB ground. 300kHz operation; tying this pin to VIN selects 750kHz
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional operation. Floating this pin selects 550kHz operation. External Soft-Start Input. Forcing this pin below 0.65V shuts
SGND (Pin 4/Pin 7):
Small-Signal Ground. This pin serves down the chip (both channels). Driving this pin to VIN or as the ground connection for most internal circuits. releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by
VIN (Pin 5/Pin 8):
Chip Signal Power Supply. This pin connecting a capacitor between this pin and ground. powers the entire chip except for the gate drivers. Exter- nally fi ltering this pin with a lowpass RC network (e.g.,
TG1/TG2 (Pins 17, 15/Pins 18, 20):
Top (PMOS) Gate R = 10Ω, C = 1μF) is suggested to minimize noise pickup, Drive Output. These pins drive the gates of the external especially in high load current applications. P-channel MOSFETs. These pins have an output swing from PGND to SENSE+.
TRACK (Pin 6/Pin 9):
Tracking Input for Second Controller. Allows the start-up of VOUT2 to track that of VOUT1 accord-
SYNC/FCB (Pin 18/Pin 21):
This pin performs three func- ing to a ratio established by a resistor divider on VOUT1 tions: 1) auxiliary winding feedback input, 2) external connected to the TRACK pin. For one-to-one tracking of clock synchronization input for phase-locked loop, and VOUT1 and VOUT2 during start-up, a resistor divider with 3) pulse-skipping operation or forced continuous mode 37362fb 6
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Undervoltage Lockout Threshold Shutdown Quiescent Current RUN/SS Start-Up Current vs Temperature vs Input Voltage vs Input Voltage
2.50 20 0.9 RUN/SS = 0V RUN/SS = 0V 18 2.45 0.8 VIN RISING 16 0.7 2.40 14 0.6 2.35 12 0.5 ) VOLTAGE (V) 2.30 10 IN VIN FALLING 0.4 8 2.25 0.3 6 INPUT (V 2.20 SHUTDOWN CURRENT (μA) 4 0.2 2.15 2 RUN/SS PIN PULL-UP CURRENT (μA) 0.1 2.10 0 0 –60 –40 –20 0 20 40 60 80 100 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 TEMPERATURE (°C) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 37362 G16 37362 G17 37362 G18
PIN FUNCTIONS (QFN/SSOP Package) ITH1/ ITH2 (Pins 1, 8/Pins 4, 11):
Current Threshold and values equal to those connected to VFB2 from VOUT2 should Error Amplifi er Compensation Point. Nominal operating be used to connect to TRACK from VOUT1. range on these pins is from 0.7V to 2V. The voltage on
PGOOD (Pin 9/Pin 12):
Power Good Output Voltage Moni- these pins determines the threshold of the main current tor Open-Drain Logic Output. This pin is pulled to ground comparator. when the voltage on either feedback pin (VFB1, VFB2) is
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter. not within ±13.3% of its nominal set point. When synchronizing to an external clock, this pin serves as
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23):
Power the lowpass fi lter point for the phase-locked loop. Normally Ground. These pins serve as the ground connection for a series RC is connected between this pin and ground. the gate drivers and the negative input to the reverse cur- When not synchronizing to an external clock, this pin serves rent comparators. The Exposed Pad must be soldered to as the frequency select input. Tying this pin to GND selects PCB ground. 300kHz operation; tying this pin to VIN selects 750kHz
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional operation. Floating this pin selects 550kHz operation. External Soft-Start Input. Forcing this pin below 0.65V shuts
SGND (Pin 4/Pin 7):
Small-Signal Ground. This pin serves down the chip (both channels). Driving this pin to VIN or as the ground connection for most internal circuits. releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by
VIN (Pin 5/Pin 8):
Chip Signal Power Supply. This pin connecting a capacitor between this pin and ground. powers the entire chip except for the gate drivers. Exter- nally fi ltering this pin with a lowpass RC network (e.g.,
TG1/TG2 (Pins 17, 15/Pins 18, 20):
Top (PMOS) Gate R = 10Ω, C = 1μF) is suggested to minimize noise pickup, Drive Output. These pins drive the gates of the external especially in high load current applications. P-channel MOSFETs. These pins have an output swing from PGND to SENSE+.
TRACK (Pin 6/Pin 9):
Tracking Input for Second Controller. Allows the start-up of VOUT2 to track that of VOUT1 accord-
SYNC/FCB (Pin 18/Pin 21):
This pin performs three func- ing to a ratio established by a resistor divider on VOUT1 tions: 1) auxiliary winding feedback input, 2) external connected to the TRACK pin. For one-to-one tracking of clock synchronization input for phase-locked loop, and VOUT1 and VOUT2 during start-up, a resistor divider with 3) pulse-skipping operation or forced continuous mode 37362fb 6