Datasheet LTC3827 (Analog Devices) - 8

LTC3827
PIN FUNCTIONS SENSE1–, SENSE2– (Pins 1, 9):
The (–) Input to the Dif-
INTVCC (Pin 19):
Output of the Internal Linear Low Dropout ferential Current Comparators. Regulator. The driver and control circuits are powered
PLLLPF (Pin 2):
The phase-locked loop’s lowpass fi lter is from this voltage source. Must be decoupled to power tied to this pin when synchronizing to an external clock. ground with a minimum of 4.7μF tantalum or other low Alternatively, tie this pin to GND, INTV ESR capacitor. CC or leave fl oating to select 250kHz, 530kHz or 400kHz switching frequency.
EXTVCC (Pin 20):
External Power Input to an Internal LDO
PHASMD (Pin 3):
Control Input to Phase Selector which Connected to INTVCC. This LDO supplies INTVCC power, determines the phase relationships between controller 1, bypassing the internal LDO powered from VIN whenever controller 2 and the CLKOUT signal. EXTVCC is higher than 4.7V. See EXTVCC Connection in the Applications Information section. Do not exceed 10V
CLKOUT (Pin 4):
Output Clock Signal available to daisy- on this pin. chain other controller ICs for additional MOSFET driver stages/phases.
PGND (Pin 21):
Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs,
PLLIN/MODE (Pin 5):
External Synchronization Input to anodes of the Schottky rectifi ers and the (–) terminal(s) Phase Detector and Forced Continuous Control Input. When of CIN. an external clock is applied to this pin, the phase-locked
V
loop will force the rising TG1 signal to be synchronized
IN (Pin 22):
Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. with the rising edge of the external clock. In this case, an R-C fi lter must be connected to the PLLLPF pin. When
BG1, BG2 (Pins 23, 18):
High Current Gate Drives for Bot- not synchronizing to an external clock, this input, which tom (Synchronous) N-Channel MOSFETs. Voltage swing acts on both controllers, determines how the LTC3827 at these pins is from ground to INTVCC. operates at light loads. Pulling this pin below 0.7V selects
BOOST1, BOOST2 (Pins 24, 17):
Bootstrapped Supplies Burst Mode operation. Tying this pin to INTVCC forces to the Topside Floating Drivers. Capacitors are connected continuous inductor current operation. Tying this pin to between the BOOST and SW pins and Schottky diodes are a voltage greater than 0.9V and less than INTVCC –1.2V tied between the BOOST and INTV selects pulse skipping operation. CC pins. Voltage swing at the BOOST pins is from INTVCC to (VIN + INTVCC).
SGND (Pins 6, 33):
Small-Signal Ground common
SW1, SW2 (Pins 25, 16):
Switch Node Connections to to both controllers, must be routed separately from Inductors. Voltage swing at these pins is from a Schottky high current grounds to the common (–) terminals diode (external) voltage drop below ground to V of the C IN. IN capacitors. The Exposed Pad is SGND. It must be soldered to PCB ground for rated thermal
TG1, TG2 (Pins 26, 15):
High Current Gate Drives for performance. Top N-Channel MOSFETs. These are the outputs of fl oat- ing drivers with a voltage swing equal to INTV
RUN1, RUN2 (Pins 7, 8):
Digital Run Control Inputs for CC – 0.5V superimposed on the switch node voltage SW. Each Controller. Forcing either of these pins below 0.7V shuts down that controller. Forcing both of these pins below
PGOOD1 (Pin 27):
Open-Drain Logic Output. PGOOD1 is 0.7V shuts down the entire LTC3827, reducing quiescent pulled to ground when the voltage on the VFB1 pin is not current to approximately 8μA. within ±10% of its set point.
FOLDDIS (Pin 14):
Foldback Current Disable Input Pin.
PGOOD2 (Pin 28):
Open-Drain Logic Output. PGOOD2 Driving this pin high (to INTVCC) disables foldback current is pulled to ground when the voltage on VFB2 pin is not limiting during short-circuit or overcurrent conditions. within ±10% of its set point. 3827ff 8