Datasheet LTC3836 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | Dual 2-Phase, No RSENSE Low VIN Synchronous Controller |
| Seiten / Seite | 30 / 6 — PIN FUNCTIONS (GN Package)/(UFD Package). SW1/SW2 (Pins 1, 14)/(Pins 26, … |
| Dateiformat / Größe | PDF / 474 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS (GN Package)/(UFD Package). SW1/SW2 (Pins 1, 14)/(Pins 26, 11):. NC (Pins 2, 18)/(Pins 16, 28):
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LTC3836
PIN FUNCTIONS (GN Package)/(UFD Package) SW1/SW2 (Pins 1, 14)/(Pins 26, 11):
Switch Node smaller of 0.6V or the voltage on the TRACK/SS2 pin. An Connection to Inductor and External MOSFETs. Also the internal 1.5μA pull-up current source is connected to this negative input to differential peak current comparator pin. A capacitor to ground at this pin sets the ramp time and an input to the reverse current comparator. Normally to fi nal regulated output voltage. Alternatively, a resistor connected to the source of the main MOSFET, the drain of divider on another voltage supply connected to this pin the synchronous MOSFET, and the inductor. allows the LTC3836 output to track the other supply dur- ing start-up.
NC (Pins 2, 18)/(Pins 16, 28):
No Connection.
PGOOD (Pin 13)/(Pin 10):
Power-Good Output Voltage
IPRG1/IPRG2 (Pins 3, 6)/(Pins 27, 3):
Three-State Pins Monitor Open-Drain Logic Output. This pin is pulled to to Select Maximum Peak Sense Voltage Threshold. These ground when the voltage on either feedback pin (VFB1, pins select the maximum allowed voltage drop between VFB2) is not within ±13.3% of its nominal set point. the SENSE+ and SW pins (i.e., the maximum allowed drop across the external main MOSFET) for each channel. Tie
PGND (Pins 17, 22, 26)/(Pins 14, 19, 23):
Power Ground. to V These pins serve as the ground connection for the gate IN, GND or fl oat to select 202mV, 82mV, or 122mV respectively. drivers and the negative input to the reverse current comparators. The Exposed Pad must be soldered to PCB
VFB1/VFB2 (Pins 4, 11)/(Pins 1, 8):
Feedback Pins. ground. Receives the remotely sensed feedback voltage for its con- troller from an external resistor divider across the output.
RUN/SS (Pin 20)/(Pin 17):
Run Control Input and Op- tional External Soft-Start Input. Forcing this pin below
ITH1/ITH2 (Pins 5, 12)/(Pins 2, 9):
Current Threshold 0.65V shuts down the chip (both channels). Driving this and Error Amplifi er Compensation Point. Nominal operat- pin to VIN or releasing this pin enables the chip, using ing range on these pins is from 0.7V to 2V. The voltage on the chip’s internal soft-start. An external soft-start can these pins determines the threshold of the main current be programmed by connecting a capacitor between this comparator. pin and ground.
PLLLPF (Pin 7)/(Pin 4):
Frequency Set/PLL Lowpass
TG1/TG2 (Pins 23, 21)/(Pins 20, 18):
Top Gate Drive Filter. When synchronizing to an external clock, this pin Output. These pins drive the gates of the external topside serves as the lowpass fi lter point for the phase-locked MOSFETs. These pins have an output swing from PGND loop. Normally a series RC is connected between this pin to BOOST. and ground.
SYNC/FCB (Pin 24)/(Pin 21):
This pin performs two When not synchronizing to an external clock, this pin serves functions: 1) external clock synchronization input for as the frequency select input. Tying this pin to GND selects phase-locked loop, and 2) pulse-skipping operation or 300kHz operation; tying this pin to VIN selects 750kHz forced continuous mode select. To synchronize with an operation. Floating this pin selects 550kHz operation. external clock using the PLL, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz. To
SGND (Pin 8)/(Pin 5):
Small-Signal Ground. This pin serves select pulse-skipping operation at light loads, tie this as the ground connection for most internal circuits. pin to VIN. Grounding this pin selects forced continuous
VIN (Pin 9)/(Pin 6):
Small-Signal Power Supply. This operation, which allows the inductor current to reverse. pin powers the entire chip except for the gate drivers. When synchronized to an external clock, pulse-skipping Externally fi ltering this pin with a lowpass RC network operation is enabled at light loads. (e.g., R = 10Ω, C = 1μF) is suggested to minimize noise
BG1/BG2 (Pins 25, 19)/(Pins 22, 15):
Bottom Gate pickup, especially in high load current applications. Drive Output. These pins drive the gates of the external
TRACK/SS2 (Pin 10)/(Pin 7):
Channel 2 Tracking and Soft- synchronous MOSFETs. These pins have an output swing Start Input. The LTC3836 regulates the VFB2 voltage to the from PGND to BOOST. 3836fb 6 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
PIN FUNCTIONS (GN Package)/(UFD Package) SW1/SW2 (Pins 1, 14)/(Pins 26, 11):
Switch Node smaller of 0.6V or the voltage on the TRACK/SS2 pin. An Connection to Inductor and External MOSFETs. Also the internal 1.5μA pull-up current source is connected to this negative input to differential peak current comparator pin. A capacitor to ground at this pin sets the ramp time and an input to the reverse current comparator. Normally to fi nal regulated output voltage. Alternatively, a resistor connected to the source of the main MOSFET, the drain of divider on another voltage supply connected to this pin the synchronous MOSFET, and the inductor. allows the LTC3836 output to track the other supply dur- ing start-up.
NC (Pins 2, 18)/(Pins 16, 28):
No Connection.
PGOOD (Pin 13)/(Pin 10):
Power-Good Output Voltage
IPRG1/IPRG2 (Pins 3, 6)/(Pins 27, 3):
Three-State Pins Monitor Open-Drain Logic Output. This pin is pulled to to Select Maximum Peak Sense Voltage Threshold. These ground when the voltage on either feedback pin (VFB1, pins select the maximum allowed voltage drop between VFB2) is not within ±13.3% of its nominal set point. the SENSE+ and SW pins (i.e., the maximum allowed drop across the external main MOSFET) for each channel. Tie
PGND (Pins 17, 22, 26)/(Pins 14, 19, 23):
Power Ground. to V These pins serve as the ground connection for the gate IN, GND or fl oat to select 202mV, 82mV, or 122mV respectively. drivers and the negative input to the reverse current comparators. The Exposed Pad must be soldered to PCB
VFB1/VFB2 (Pins 4, 11)/(Pins 1, 8):
Feedback Pins. ground. Receives the remotely sensed feedback voltage for its con- troller from an external resistor divider across the output.
RUN/SS (Pin 20)/(Pin 17):
Run Control Input and Op- tional External Soft-Start Input. Forcing this pin below
ITH1/ITH2 (Pins 5, 12)/(Pins 2, 9):
Current Threshold 0.65V shuts down the chip (both channels). Driving this and Error Amplifi er Compensation Point. Nominal operat- pin to VIN or releasing this pin enables the chip, using ing range on these pins is from 0.7V to 2V. The voltage on the chip’s internal soft-start. An external soft-start can these pins determines the threshold of the main current be programmed by connecting a capacitor between this comparator. pin and ground.
PLLLPF (Pin 7)/(Pin 4):
Frequency Set/PLL Lowpass
TG1/TG2 (Pins 23, 21)/(Pins 20, 18):
Top Gate Drive Filter. When synchronizing to an external clock, this pin Output. These pins drive the gates of the external topside serves as the lowpass fi lter point for the phase-locked MOSFETs. These pins have an output swing from PGND loop. Normally a series RC is connected between this pin to BOOST. and ground.
SYNC/FCB (Pin 24)/(Pin 21):
This pin performs two When not synchronizing to an external clock, this pin serves functions: 1) external clock synchronization input for as the frequency select input. Tying this pin to GND selects phase-locked loop, and 2) pulse-skipping operation or 300kHz operation; tying this pin to VIN selects 750kHz forced continuous mode select. To synchronize with an operation. Floating this pin selects 550kHz operation. external clock using the PLL, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz. To
SGND (Pin 8)/(Pin 5):
Small-Signal Ground. This pin serves select pulse-skipping operation at light loads, tie this as the ground connection for most internal circuits. pin to VIN. Grounding this pin selects forced continuous
VIN (Pin 9)/(Pin 6):
Small-Signal Power Supply. This operation, which allows the inductor current to reverse. pin powers the entire chip except for the gate drivers. When synchronized to an external clock, pulse-skipping Externally fi ltering this pin with a lowpass RC network operation is enabled at light loads. (e.g., R = 10Ω, C = 1μF) is suggested to minimize noise
BG1/BG2 (Pins 25, 19)/(Pins 22, 15):
Bottom Gate pickup, especially in high load current applications. Drive Output. These pins drive the gates of the external
TRACK/SS2 (Pin 10)/(Pin 7):
Channel 2 Tracking and Soft- synchronous MOSFETs. These pins have an output swing Start Input. The LTC3836 regulates the VFB2 voltage to the from PGND to BOOST. 3836fb 6 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS