Datasheet ADP1829 (Analog Devices) - 4

ADP1829 Data Sheet Parameter Conditions Min Typ Max Unit
OSCILLATOR Oscillator Frequency SYNC = FREQ = GND (fSW = fOSC) 240 300 370 kHz SYNC = GND, FREQ = VREG (fSW = fOSC) 480 600 720 kHz SYNC Synchronization Range2 FREQ = GND, SYNC = 600 kHz to 1.2 MHz (fSW = fSYNC/2) 300 600 kHz FREQ = VREG, SYNC = 1.2 MHz to 2 MHz (fSW = fSYNC/2) 600 1000 kHz SYNC Minimum Input Pulse Width 200 ns CURRENT SENSE CSL1, CSL2 Threshold Voltage Relative to PGND −30 0 +30 mV CSL1, CSL2 Output Current CSL1, CSL2 = PGND 44 50 56 μA Current Sense Blanking Period 100 ns GATE DRIVERS DH1, DH2 Rise Time CDH = 3 nF, VBST − VSW = 5 V 15 ns DH1, DH2 Fall Time CDH = 3 nF, VBST − VSW = 5 V 10 ns DL1, DL2 Rise Time CDL = 3 nF 15 ns DL1, DL2 Fall Time CDL = 3 nF 10 ns DH to DL, DL to DH Dead Time 40 ns LOGIC THRESHOLDS SYNC, FREQ, LDOSD Input High Voltage 2.2 V SYNC, FREQ, LDOSD Input Low Voltage 0.4 V SYNC, FREQ Input Leakage Current SYNC, FREQ = 0 V to 5.5 V 1 μA LDOSD Pull-Down Resistance 100 kΩ EN1, EN2 Input High Voltage IN = 3.0 V to 20 V 2.0 V EN1, EN2 Input Low Voltage IN = 3.0 V to 20 V 0.8 V EN1, EN2 Current Source EN1, EN2 = 0 V to 3.0 V −0.3 −0.6 −1.5 μA EN1, EN2 Input Impedance to 5 V Zener EN1, EN2 = 5.5 V to 20 V 100 kΩ THERMAL SHUTDOWN Thermal Shutdown Threshold3 145 °C Thermal Shutdown Hysteresis3 15 °C POWER GOOD FB1, UV2 Overvoltage Threshold VFB1, VUV2 rising 750 mV FB1, UV2 Overvoltage Hysteresis 50 mV FB1, UV2 Undervoltage Threshold VFB1, VUV2 rising 550 mV FB1, UV2 Undervoltage Hysteresis 50 mV POK1, POK2 Propagation Delay 8 μs POK1, POK2 Off Leakage Current VPOK1, VPOK2 = 5.5 V 1 μA POK1, POK2 Output Low Voltage IPOK1, IPOK2 = 10 mA 150 500 mV UV2 Input Bias Current 10 100 nA 1 Not recommended to use the LDO in dropout when VIN < 5.5 V because of the dropout voltage. Connect IN to VREG when VIN < 5.5 V. 2 SYNC input frequency is 2× single-channel switching frequency. The SYNC frequency is divided by 2 and the separate phases were used to clock the control ers. 3 Guaranteed by design and not subject to production test. Rev. D | Page 4 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT POWER START-UP LOGIC INTERNAL LINEAR REGULATOR OSCILLATOR AND SYNCHRONIZATION ERROR AMPLIFIER SOFT START POWER OK INDICATOR TRACKING MOSFET DRIVERS CURRENT LIMIT APPLICATIONS INFORMATION SELECTING THE INPUT CAPACITOR Selecting the Output LC Filter SELECTING THE MOSFETS SETTING THE CURRENT LIMIT FEEDBACK VOLTAGE DIVIDER COMPENSATING THE VOLTAGE MODE BUCK REGULATOR Type II Compensator Type III Compensator SOFT START VOLTAGE TRACKING COINCIDENT TRACKING RATIOMETRIC TRACKING Setting the Channel 2 Undervoltage Threshold for Ratiometric Tracking THERMAL CONSIDERATIONS PCB LAYOUT GUIDELINES LFCSP PACKAGE CONSIDERATIONS APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE