Datasheet LTC3826-1 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 30µA IQ, Dual, 2-Phase Synchronous Step-Down Controller |
| Seiten / Seite | 32 / 7 — TYPICAL PERFORMANCE CHARACTERISTICS. Undervoltage Lockout Threshold. … |
| Dateiformat / Größe | PDF / 438 Kb |
| Dokumentensprache | Englisch |
TYPICAL PERFORMANCE CHARACTERISTICS. Undervoltage Lockout Threshold. Oscillator Frequency. Shutdown Current. vs Temperature
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LTC3826-1
TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout Threshold Oscillator Frequency Shutdown Current vs Temperature vs Input Voltage vs Temperature
4.2 392 6 4.1 390 5 4.0 RISING 3.9 388 4 3.8 3.7 386 3 VOLTAGE (V) FALLING CC 3.6 384 2 INTV 3.5 SHUTDOWN CURRENT (μA) 3.4 OSCILLATOR FREQUENCY (kHz) 382 1 3.3 3.2 380 0 –45 –30 –15 0 15 30 45 60 75 90 5 10 15 20 25 30 35 –45 –30 –15 0 15 30 45 60 75 90 TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C) 38261 G25 38261 G26 38261 G27
PIN FUNCTIONS ITH1, ITH2 (Pins 1, 13):
Error Amplifi er Outputs and
PLLIN/MODE (Pin 6):
External Synchronization Input to Switching Regulator Compensation Points. Each associ- Phase Detector and Forced Continuous Control Input. When ated channel’s current comparator trip point increases an external clock is applied to this pin, the phase-locked with this control voltage. loop will force the rising TG1 signal to be synchronized with the rising edge of the external clock. In this case, an
VFB1, VFB2 (Pins 2, 12):
Receives the remotely sensed R-C fi lter must be connected to the PLLLPF pin. When feedback voltage for each controller from an external not synchronizing to an external clock, this input, which resistive divider across the output. acts on both controllers, determines how the LTC3826-1
SENSE1+, SENSE2+ (Pins 3, 11):
The (+) Input to the operates at light loads. Pulling this pin below 0.7V selects Differential Current Comparators. The ITH pin voltage and Burst Mode operation. Tying this pin to INTVCC forces controlled offsets between the SENSE– and SENSE+ pins in continuous inductor current operation. Tying this pin to conjunction with RSENSE set the current trip threshold. a voltage greater than 0.9V and less than INTVCC –1.2V
SENSE1–, SENSE2– (Pins 4, 10):
The (–) Input to the selects pulse skipping operation. Differential Current Comparators.
SGND (Pin 7):
Small-signal Ground common to both
PLLLPF (Pin 5):
The phase-locked loop’s lowpass fi lter is controllers, must be routed separately from high cur- tied to this pin when synchronizing to an external clock. rent grounds to the common (–) terminals of the CIN Alternatively, tie this pin to GND, INTV capacitors. CC or leave fl oating to select 250kHz, 530kHz or 390kHz switching frequency. 38261fb 7
TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout Threshold Oscillator Frequency Shutdown Current vs Temperature vs Input Voltage vs Temperature
4.2 392 6 4.1 390 5 4.0 RISING 3.9 388 4 3.8 3.7 386 3 VOLTAGE (V) FALLING CC 3.6 384 2 INTV 3.5 SHUTDOWN CURRENT (μA) 3.4 OSCILLATOR FREQUENCY (kHz) 382 1 3.3 3.2 380 0 –45 –30 –15 0 15 30 45 60 75 90 5 10 15 20 25 30 35 –45 –30 –15 0 15 30 45 60 75 90 TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C) 38261 G25 38261 G26 38261 G27
PIN FUNCTIONS ITH1, ITH2 (Pins 1, 13):
Error Amplifi er Outputs and
PLLIN/MODE (Pin 6):
External Synchronization Input to Switching Regulator Compensation Points. Each associ- Phase Detector and Forced Continuous Control Input. When ated channel’s current comparator trip point increases an external clock is applied to this pin, the phase-locked with this control voltage. loop will force the rising TG1 signal to be synchronized with the rising edge of the external clock. In this case, an
VFB1, VFB2 (Pins 2, 12):
Receives the remotely sensed R-C fi lter must be connected to the PLLLPF pin. When feedback voltage for each controller from an external not synchronizing to an external clock, this input, which resistive divider across the output. acts on both controllers, determines how the LTC3826-1
SENSE1+, SENSE2+ (Pins 3, 11):
The (+) Input to the operates at light loads. Pulling this pin below 0.7V selects Differential Current Comparators. The ITH pin voltage and Burst Mode operation. Tying this pin to INTVCC forces controlled offsets between the SENSE– and SENSE+ pins in continuous inductor current operation. Tying this pin to conjunction with RSENSE set the current trip threshold. a voltage greater than 0.9V and less than INTVCC –1.2V
SENSE1–, SENSE2– (Pins 4, 10):
The (–) Input to the selects pulse skipping operation. Differential Current Comparators.
SGND (Pin 7):
Small-signal Ground common to both
PLLLPF (Pin 5):
The phase-locked loop’s lowpass fi lter is controllers, must be routed separately from high cur- tied to this pin when synchronizing to an external clock. rent grounds to the common (–) terminals of the CIN Alternatively, tie this pin to GND, INTV capacitors. CC or leave fl oating to select 250kHz, 530kHz or 390kHz switching frequency. 38261fb 7