Datasheet LTC1879 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 1.2A Synchronous Step-Down Regulator with 15µA Quiescent Current |
| Seiten / Seite | 20 / 9 — OPERATIO. (Refer to Block Diagram). Power Good Indicator. Low Dropout … |
| Dateiformat / Größe | PDF / 268 Kb |
| Dokumentensprache | Englisch |
OPERATIO. (Refer to Block Diagram). Power Good Indicator. Low Dropout Operation. Low Supply Operation. Short-Circuit Protection
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LTC1879
U OPERATIO (Refer to Block Diagram) Power Good Indicator Low Dropout Operation
The power good function monitors the output voltage in all When the input supply voltage decreases toward the modes of operation. Its open-drain output is pulled low output voltage in a buck regulator, the duty cycle in- when the output voltage is not within ±7.5% of its nomi- creases toward the maximum on-time. Further reduction nally regulated voltage. The feedback voltage is filtered of the supply voltage forces the main switch to remain on before it is fed to a power good window comparator in for more than one cycle until it reaches 100% duty cycle. order to prevent false tripping of the power good signal The output voltage will then be determined by the input during fast transients. The window comparator monitors voltage minus the voltage drop across the top MOSFET the output voltage even in Burst Mode operation. In and the inductor. shutdown mode, open drain is actively pulled low to indicate that the output voltage is invalid.
Low Supply Operation
The LTC1879 is designed to operate down to an input
Short-Circuit Protection
supply voltage of 2.65V although the maximum allowable When the output is shorted to ground, the frequency of output current is reduced at this low voltage. Figure 2 the oscillator is reduced to about 80kHz, 1/7 the nominal shows the reduction in the maximum output current as a frequency. This frequency foldback ensures that the in- function of input voltage. ductor current has more time to decay, thereby preventing Another important detail to remember is that at low input runaway. The oscillator’s frequency will progressively supply voltages, the R increase to 550kHz (or to the synchronized frequency) DS(ON) of the P-channel switch increases. Therefore, the user should calculate the power when VFB rises above 0.3V. dissipation when the LTC1879 is used at 100% duty cycle with low supply voltage (see Thermal Considerations in
Frequency Synchronization
the Applications Information section). The LTC1879 can be synchronized to an external clock source connected to the SYNC/MODE pin. The turn-on of the top MOSFET is synchronized to the rising edge of the 1800 external clock. 1600 When the LTC1879 is clocked by an external source, Burst VOUT = 2.5V 1400 Mode operation is disabled. In this synchronized mode, VOUT = 1.8V 1200 when the output load current is very low, current compara- VOUT = 3.1V tor, I 1000 COMP, may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. 800 Increasing the output load slightly allows constant fre- MAXIMUM OUTPUT CURRENT (mA) 600 quency PWM operation to resume. 400 Frequency synchronization is inhibited when the feedback 2 3 4 5 6 7 8 9 10 voltage V INPUT VOLTAGE (V) FB is below 0.6V. This prevents the external clock 1879 F02 from interfering with the frequency foldback for short- circuit protection.
Figure 2. Maximum Output Current vs Input Voltage
1879f 9
U OPERATIO (Refer to Block Diagram) Power Good Indicator Low Dropout Operation
The power good function monitors the output voltage in all When the input supply voltage decreases toward the modes of operation. Its open-drain output is pulled low output voltage in a buck regulator, the duty cycle in- when the output voltage is not within ±7.5% of its nomi- creases toward the maximum on-time. Further reduction nally regulated voltage. The feedback voltage is filtered of the supply voltage forces the main switch to remain on before it is fed to a power good window comparator in for more than one cycle until it reaches 100% duty cycle. order to prevent false tripping of the power good signal The output voltage will then be determined by the input during fast transients. The window comparator monitors voltage minus the voltage drop across the top MOSFET the output voltage even in Burst Mode operation. In and the inductor. shutdown mode, open drain is actively pulled low to indicate that the output voltage is invalid.
Low Supply Operation
The LTC1879 is designed to operate down to an input
Short-Circuit Protection
supply voltage of 2.65V although the maximum allowable When the output is shorted to ground, the frequency of output current is reduced at this low voltage. Figure 2 the oscillator is reduced to about 80kHz, 1/7 the nominal shows the reduction in the maximum output current as a frequency. This frequency foldback ensures that the in- function of input voltage. ductor current has more time to decay, thereby preventing Another important detail to remember is that at low input runaway. The oscillator’s frequency will progressively supply voltages, the R increase to 550kHz (or to the synchronized frequency) DS(ON) of the P-channel switch increases. Therefore, the user should calculate the power when VFB rises above 0.3V. dissipation when the LTC1879 is used at 100% duty cycle with low supply voltage (see Thermal Considerations in
Frequency Synchronization
the Applications Information section). The LTC1879 can be synchronized to an external clock source connected to the SYNC/MODE pin. The turn-on of the top MOSFET is synchronized to the rising edge of the 1800 external clock. 1600 When the LTC1879 is clocked by an external source, Burst VOUT = 2.5V 1400 Mode operation is disabled. In this synchronized mode, VOUT = 1.8V 1200 when the output load current is very low, current compara- VOUT = 3.1V tor, I 1000 COMP, may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. 800 Increasing the output load slightly allows constant fre- MAXIMUM OUTPUT CURRENT (mA) 600 quency PWM operation to resume. 400 Frequency synchronization is inhibited when the feedback 2 3 4 5 6 7 8 9 10 voltage V INPUT VOLTAGE (V) FB is below 0.6V. This prevents the external clock 1879 F02 from interfering with the frequency foldback for short- circuit protection.
Figure 2. Maximum Output Current vs Input Voltage
1879f 9