Datasheet LTC3408 (Analog Devices) - 10

LTC3408
U U W U APPLICATIO S I FOR ATIO
1 100 junction temperature of the part. If the junction tempera- 90 ture reaches approximately 150°C, both power switches 80 will be turned off and the SW node will become high 70 EFFICIENCY (%) 0.1 impedance. 60 50 To prevent the LTC3408 from exceeding the maximum 40 junction temperature, the user will need to do some POWER LOST (W) 0.01 30 thermal analysis. The goal of the thermal analysis is to VOUT = 1.2V 20 determine whether the power dissipated exceeds the VOUT = 1.5V VOUT = 1.8V 10 maximum junction temperature of the part. The tempera- VOUT = 2.5V 0.01 0 ture rise is given by: 1 10 100 1000 LOAD CURRENT (mA) TR = (PD)(θJA) 3408 F04 where PD is the power dissipated by the regulator and θJA
Figure 4. Power Lost vs Load Current
is the thermal resistance from the junction of the die to the IGATECHG = f(QT + QB), where QT and QB are the gate ambient temperature. charges of the internal top and bottom switches. Both the The junction temperature, TJ, is given by: DC bias and gate charge losses are proportional to VIN, thus, their effects will be more pronounced at higher TJ = TA + TR supply voltages. (The gate charge of the bypass FET is, where TA is the ambient temperature. of course, negligible because it is infrequently cycled.) As an example, consider the LTC3408 in dropout at an 2. I2R losses are calculated from the resistances of the input voltage of 2.7V, a load current of 600mA (0.9V ≤ VREF internal switches, RSW, and external inductor RL. In con- < 1.2V) and an ambient temperature of 70°C. With VREF < tinuous mode, the average output current flowing through 1.2V, the entire 600mA flows through the main P-channel inductor L is “chopped” between the main switch and the FET. From the typical performance graph of switch resis- synchronous switch. Thus, the series resistance looking tance, the RDS(ON) of the P-channel switch at 70°C is into the SW pin is a function of both top and bottom approximately 0.52Ω. Therefore, power dissipated by the MOSFET RDS(ON) and the duty cycle (DC) as follows: part is: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) PD = (I 2 LOAD ) • RDS(ON) = 187.2mW The RDS(ON) for both the top and bottom MOSFETs can be For the 8L DFN package, the θ obtained from the Typical Performance Charateristics JA is 43°C/W. Thus, the junction temperature of the regulator is: curves. Hence, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output TJ = 70°C + (0.1872)(43) = 78°C current. which is below the maximum junction temperature of Other losses including C 125°C. IN and COUT ESR dissipative losses and inductor core losses generally account for less Modifying this example, suppose that VREF is raised to than 2% total additional loss. 1.2V or higher. This turns on the bypass P-channel FET as
Thermal Considerations
well as the main P-channel FET. Assume that the inductor’s DC resistance is 0.1Ω, the RDS(ON) of the main P-channel In most applications the LTC3408 does not dissipate switch is 0.52Ω, and the RDS(ON) of the bypass P-channel much heat due to its high efficiency. But, in applications switch is 0.08Ω. The current through the P-channel switch where the LTC3408 is running at high ambient tempera- and the inductor will be 69mA, causing power dissipation ture with low supply voltage and high duty cycles, such as of (0.069A)2 • 0.62Ω = 2.9mW. The bypass FET will in dropout, the heat dissipated may exceed the maximum 3408f 10