Datasheet LTC3447 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | I2C Controllable Buck Regulator in 3mm × 3mm DFN |
| Seiten / Seite | 16 / 6 — PI FU CTIO S. VOUT (Pin 1):. SW (Pin 6):. GND (Pin 2):. RUN (Pin 7):. FB … |
| Dateiformat / Größe | PDF / 578 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. VOUT (Pin 1):. SW (Pin 6):. GND (Pin 2):. RUN (Pin 7):. FB (Pin 3):. SCL (Pin 8):. PGOOD (Pin 4):. VCCD (Pin 9)
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Textversion des Dokuments
LTC3447
U U U PI FU CTIO S VOUT (Pin 1):
Output Voltage Sensing Pin. An internal
SW (Pin 6):
Switch Node Connector to Inductor. This pin resistor divider provides the divided down feedback refer- connects the drains of the internal main and synchronous ence for comparison. power MOSFET switches.
GND (Pin 2):
Ground for all Circuits Excluding the Internal
RUN (Pin 7):
Run Control Input. Forcing pin above 1.5V Synchronous Power NFET. enables the part. Forcing the pin below 0.3V shuts down the device. In shutdown, all functions are disabled draw-
FB (Pin 3):
Feedback Sensing Pin for the Optional External ing <1µA of supply current. Do not leave the RUN pin Feedback Resistors. Must be tied to VIN if there are no fl oating. external feedback resistors.
SCL (Pin 8):
I2C Clock Input.
PGOOD (Pin 4):
Fault Report. Open drain driver sinks cur- rent when VOUT is 10% out of tolerance. Blanking during
VCCD (Pin 9)
: I2C Power Rail. DAC changes can be enabled via the I2C.
SDA (Pin 10):
I2C Data Input.
VIN (Pin 5):
Main Supply Pin. Must be closely decoupled
Exposed Pad (Pin 11)
: Ground. Must be connected to to GND with a 2.2µF or greater capacitor. PCB ground for electrical contact and optimized thermal performance.
W BLOCK DIAGRA
VIN CIN RUN VOUT 6-BIT DAC SW VCCD SLEW SW VDAC + SOFT-START BUCK C SDA V REGULATOR OUT DAC REF I2C 1.3R – BURST SCL V MUX FB LOAD BURST R BLANK REF R1 POWER UV REF PGOOD GOOD OV REF MUX FB R2 S DAC LTC3447 3447 BD
Figure 2. LTC3447 High Level Block Diagram
3447f 6
U U U PI FU CTIO S VOUT (Pin 1):
Output Voltage Sensing Pin. An internal
SW (Pin 6):
Switch Node Connector to Inductor. This pin resistor divider provides the divided down feedback refer- connects the drains of the internal main and synchronous ence for comparison. power MOSFET switches.
GND (Pin 2):
Ground for all Circuits Excluding the Internal
RUN (Pin 7):
Run Control Input. Forcing pin above 1.5V Synchronous Power NFET. enables the part. Forcing the pin below 0.3V shuts down the device. In shutdown, all functions are disabled draw-
FB (Pin 3):
Feedback Sensing Pin for the Optional External ing <1µA of supply current. Do not leave the RUN pin Feedback Resistors. Must be tied to VIN if there are no fl oating. external feedback resistors.
SCL (Pin 8):
I2C Clock Input.
PGOOD (Pin 4):
Fault Report. Open drain driver sinks cur- rent when VOUT is 10% out of tolerance. Blanking during
VCCD (Pin 9)
: I2C Power Rail. DAC changes can be enabled via the I2C.
SDA (Pin 10):
I2C Data Input.
VIN (Pin 5):
Main Supply Pin. Must be closely decoupled
Exposed Pad (Pin 11)
: Ground. Must be connected to to GND with a 2.2µF or greater capacitor. PCB ground for electrical contact and optimized thermal performance.
W BLOCK DIAGRA
VIN CIN RUN VOUT 6-BIT DAC SW VCCD SLEW SW VDAC + SOFT-START BUCK C SDA V REGULATOR OUT DAC REF I2C 1.3R – BURST SCL V MUX FB LOAD BURST R BLANK REF R1 POWER UV REF PGOOD GOOD OV REF MUX FB R2 S DAC LTC3447 3447 BD
Figure 2. LTC3447 High Level Block Diagram
3447f 6