Datasheet LTC3410B (Analog Devices) - 7

LTC3410B
U OPERATIO (Refer to Functional Diagram) Main Control Loop
frequency. This frequency foldback ensures that the in- ductor current has more time to decay, thereby preventing The LTC3410B uses a constant frequency, current mode runaway. The oscillator’s frequency will progressively step-down architecture. Both the main (P-channel increase to 2.25MHz when V MOSFET) and synchronous (N-channel MOSFET) switches FB rises above 0V. are internal. During normal operation, the internal top
Dropout Operation
power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current com- As the input supply voltage decreases to a value approach- parator, I ing the output voltage, the duty cycle increases toward the COMP, resets the RS latch. The peak inductor current at which I maximum on-time. Further reduction of the supply volt- COMP resets the RS latch, is controlled by the output of error amplifier EA. The V age forces the main switch to remain on for more than one FB pin, described in the Pin Functions section, allows EA to receive an output cycle until it reaches 100% duty cycle. The output voltage feedback voltage from an external resistive divider. When will then be determined by the input voltage minus the the load current increases, it causes a slight decrease in voltage drop across the P-channel MOSFET and the the feedback voltage relative to the 0.8V reference, which inductor. in turn, causes the EA amplifier’s output voltage to in- Another important detail to remember is that at low input crease until the average inductor current matches the new supply voltages, the RDS(ON) of the P-channel switch load current. While the top MOSFET is off, the bottom increases (see Typical Performance Characteristics). MOSFET is turned on until either the inductor current Therefore, the user should calculate the power dissipation starts to reverse, as indicated by the current reversal when the LTC3410B is used at 100% duty cycle with low comparator IRCMP, or the beginning of the next clock cycle. input voltage (See Thermal Considerations in the Applica-
Pulse Skipping Mode Operation
tions Information section). At light loads, the inductor current may reach zero or re-
Slope Compensation and Inductor Peak Current
verse on each pulse. The bottom MOSFET is turned off by the current reversal comparator, I Slope compensation provides stability in constant fre- RCMP, and the switch voltage will ring. This is discontinuous mode operation, quency architectures by preventing subharmonic oscilla- and is normal behavior for the switching regulator. At very tions at high duty cycles. It is accomplished internally by light loads, the LTC3410B will automatically skip pulses in adding a compensating ramp to the inductor current pulse skipping mode operation to maintain output regula- signal at duty cycles in excess of 40%. Normally, this tion. Refer to LTC3410 data sheet if Burst Mode® operation results in a reduction of maximum inductor peak current is preferred. for duty cycles > 40%. However, the LTC3410B uses a patented scheme that counteracts this compensating
Short-Circuit Protection
ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. When the output is shorted to ground, the frequency of the oscillator is reduced to about 310kHz, 1/7 the nominal Burst Mode is a Registered Trademark of Linear Technology Corporation. 3410bfa 7